IBM Enterprise System/9000 Type 9121 system controller and memory subsystem design. - Brian W. Curran; Manfred H. Walz (IBM J. Res. Dev., 1991)

Switching Codes for Delta-I Noise Reduction. - C. L. Chen; Brian W. Curran (IEEE Trans. Computers, 1996)

High-Performance CMOS Circuit Techniques for the G-4 S/390 Microprocessor. - James D. Warnock; Leon J. Sigal; Brian W. Curran; Yuen H. Chan (ICCD, 1997)

Design methodology for the S/390 Parallel Enterprise Server G4 microprocessors. - Kenneth L. Shepard; Sean M. Carey; Ee Kin Cho; Brian W. Curran; Robert F. Hatch; Dale E. Hoffman; Scott A. McCabe; Gregory A. Northrop; A. E. (Rick) Seigler (IBM J. Res. Dev., 1997)

Circuit design techniques for the high-performance CMOS IBM S/390 Parallel Enterprise Server G4 microprocessor. - Leon J. Sigal; James D. Warnock; Brian W. Curran; Yuen H. Chan; Peter J. Camporese; Mark D. Mayo; William V. Huott; Daniel R. Knebel; Ching-Te Chuang; James P. Eckhardt; Philip T. Wu (IBM J. Res. Dev., 1997)

A 4.1-ns compact 54×54-b multiplier utilizing sign-select Booth encoders. - Charles F. Webb; Carl J. Anderson; Leon J. Sigal; Kenneth L. Shepard; John S. Liptay; James D. Warnock; Brian W. Curran; Barry Krumm; Mark D. Mayo; Peter J. Camporese; Eric M. Schwarz; Mark S. Farrell; et al. (IEEE J. Solid State Circuits, 1997)

Deep submicron design techniques for the 500 MHz IBM S/390 G5 custom microprocessor. - Dale E. Hoffman; Robert M. Averill III; Brian W. Curran; Yuen H. Chan; Allan H. Dansky; Robert F. Hatch; Timothy G. McNamara; Thomas J. McPherson; Gregory A. Northrop; Leon J. Sigal; Anthony Pelella; Patrick M. Williams (ICCD, 1998)

Low-Voltage 0, 25 µm CMOS Improved Power Adaptive Issue Queue for Embedded Microprocessors. - Brian W. Curran; Mary Gifaldi; Jason Martin; Alper Buyuktosunoglu; Martin Margala; David H. Albonesi (VLSI-SOC, 2001)

IBM eServer z900 high-frequency microprocessor technology, circuits, and design methodology. - Brian W. Curran; Yuen H. Chan; Philip T. Wu; Peter J. Camporese; Gregory A. Northrop; Robert F. Hatch; Lisa B. Lacey; James P. Eckhardt; David T. Hui; Howard H. Smith (IBM J. Res. Dev., 2002)

4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor. - Brian W. Curran; Bradley D. McCredie; Leonid Sigal; Eric M. Schwarz; Bruce M. Fleischer; Yuen H. Chan; D. Webber; Vaden Vaden; A. Goyal (ISSCC, 2006)

Design of the Power6 Microprocessor. - Joshua Friedrich; Bradley D. McCredie; Norman K. James; Bill Huott; Brian W. Curran; Eric Fluhr; Gaurav Mittal; Eddie Chan; Yuen H. Chan; Donald W. Plass; Sam G. Chu; Hung Q. Le; et al. (ISSCC, 2007)

Power-constrained high-frequency circuits for the IBM POWER6 microprocessor. - Brian W. Curran; Eric Fluhr; Jose Paredes; Leon J. Sigal; Joshua Friedrich; Yiu-Hing Chan; Charlie Hwang (IBM J. Res. Dev., 2007)

IBM zEnterprise 196 processor. - Brian W. Curran (Hot Chips Symposium, 2010)

A 5.2GHz microprocessor chip for the IBM zEnterprise™ system. - James D. Warnock; Y. Chan; William V. Huott; Sean M. Carey; Michael F. Fee; Huajun Wen; Mary Jo Saccamango; Frank Malgioglio; Patrick J. Meaney; Donald W. Plass; Yuen H. Chan; Mark D. Mayo; et al. (ISSCC, 2011)

The zEnterprise 196 System and Microprocessor. - Brian W. Curran; Lee Eisen; Eric M. Schwarz; Pak-kin Mak; James D. Warnock; Patrick J. Meaney; Michael F. Fee (IEEE Micro, 2011)

IBM zEnterprise 196 microprocessor and cache subsystem. - Fadi Busaba; Michael A. Blake; Brian W. Curran; Michael F. Fee; Christian Jacobi 002; Pak-kin Mak; Brian R. Prasky; Craig R. Walters (IBM J. Res. Dev., 2012)

4.1 22nm Next-generation IBM System z microprocessor. - James D. Warnock; Brian W. Curran; John Badar; Gregory Fredeman; Donald W. Plass; Yuen H. Chan; Sean M. Carey; Gerard Salem; Friedrich Schroeder; Frank Malgioglio; Guenter Mayer; Christopher J. Berry; et al. (ISSCC, 2015)

The IBM z13 multithreaded microprocessor. - Brian W. Curran; Christian Jacobi 002; J. J. Bonanno; D. A. Schroter; K. J. Alexander; A. Puranik; Markus M. Helms (IBM J. Res. Dev., 2015)

Robust power management in the IBM z13. - Tobias Webel; Preetham M. Lobo; Ramon Bertran; Gerard Salem; Malcolm Allen-Ware; Richard F. Rizzolo; Sean M. Carey; Thomas Strach; Alper Buyuktosunoglu; Charles Lefurgy; Pradip Bose; Ricardo Nigaglioni; et al. (IBM J. Res. Dev., 2015)

Across the Stack Opportunities for Deep Learning Acceleration. - Vijayalakshmi Srinivasan; Bruce M. Fleischer; Sunil Shukla; Matthew M. Ziegler; Joel Silberman; Jinwook Oh; Jungwook Choi; Silvia M. Mueller; Ankur Agrawal; Tina Babinsky; Nianzheng Cao; Chia-Yu Chen; et al. (ISLPED, 2018)

A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference. - Bruce M. Fleischer; Sunil Shukla; Matthew M. Ziegler; Joel Silberman; Jinwook Oh; Vijayalakshmi Srinivasan; Jungwook Choi; Silvia M. Mueller; Ankur Agrawal; Tina Babinsky; Nianzheng Cao; Chia-Yu Chen; et al. (VLSI Circuits, 2018)

A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference. - Jinwook Oh; Sae Kyu Lee; Mingu Kang; Matthew M. Ziegler; Joel Silberman; Ankur Agrawal; Swagath Venkataramani; Bruce M. Fleischer; Michael Guillorn; Jungwook Choi; Wei Wang 333; Silvia M. Mueller; et al. (VLSI Circuits, 2020)

Efficient AI System Design With Cross-Layer Approximate Computing. - Swagath Venkataramani; Xiao Sun 013; Naigang Wang; Chia-Yu Chen; Jungwook Choi; Mingu Kang; Ankur Agarwal; Jinwook Oh; Shubham Jain; Tina Babinsky; Nianzheng Cao; Thomas W. Fox; et al. (Proc. IEEE, 2020)

RaPiD: AI Accelerator for Ultra-low Precision Training and Inference. - Swagath Venkataramani; Vijayalakshmi Srinivasan; Wei Wang 333; Sanchari Sen; Jintao Zhang; Ankur Agrawal; Monodeep Kar; Shubham Jain; Alberto Mannari; Hoang Tran; Yulong Li; Eri Ogawa; et al. (ISCA, 2021)

A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling. - Ankur Agrawal; Sae Kyu Lee; Joel Silberman; Matthew M. Ziegler; Mingu Kang; Swagath Venkataramani; Nianzheng Cao; Bruce M. Fleischer; Michael Guillorn; Matt Cohen; Silvia M. Mueller; Jinwook Oh; et al. (ISSCC, 2021)

A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling. - Sae Kyu Lee; Ankur Agrawal; Joel Silberman; Matthew M. Ziegler; Mingu Kang; Swagath Venkataramani; Nianzheng Cao; Bruce M. Fleischer; Michael Guillorn; Matthew Cohen; Silvia M. Mueller; Jinwook Oh; et al. (IEEE J. Solid State Circuits, 2022)