Effectiveness of Individual and Dyadic Training Protocols: The Influence of Trainee Interaction Anxiety. - Winfred Arthur; Brian Young; Jeffrey A. Jordan; Wayne L. Shebilske (Hum. Factors, 1996)

On-chip inductance modeling and analysis. - Kaushik Gala; Vladimir Zolotov; Rajendran Panda; Brian Young; Junfeng Wang; David T. Blaauw (DAC, 2000)

Model and analysis for combined package and on-chip power grid simulation. - Rajendran Panda; David T. Blaauw; Rajat Chaudhry; Vladimir Zolotov; Brian Young; Ravi Ramaraju (ISLPED, 2000)

The Cross-Breeding of Dictionaries. - Adam L. Meyers; Ruth Reeves; Catherine Macleod; Rachel Szekely; Veronika Zielinska; Brian Young (LREC, 2004)

Annotating Noun Argument Structure for NomBank. - Adam L. Meyers; Ruth Reeves; Catherine Macleod; Rachel Szekely; Veronika Zielinska; Brian Young; Ralph Grishman (LREC, 2004)

The NomBank Project: An Interim Report. - Adam L. Meyers; Ruth Reeves; Catherine Macleod; Rachel Szekely; Veronika Zielinska; Brian Young; Ralph Grishman (FCP@NAACL-HLT, 2004)

A 2.4ps resolution 2.1mW second-order noise-shaped time-to-digital converter with 3.2ns range in 1MHz bandwidth. - Brian Young; Sunwoo Kwon; Amr Elshazly; Pavan Kumar Hanumolu (CICC, 2010)

A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration. - Amr Elshazly; Rajesh Inti; Wenjing Yin; Brian Young; Pavan Kumar Hanumolu (ISSCC, 2011)

A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS. - Rajesh Inti; Amr Elshazly; Brian Young; Wenjing Yin; Marcel A. Kossel; Thomas Toifl; Pavan Kumar Hanumolu (ISSCC, 2011)

A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration. - Amr Elshazly; Rajesh Inti; Wenjing Yin; Brian Young; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2011)

A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery. - Wenjing Yin; Rajesh Inti; Amr Elshazly; Mrunmay Talegaonkar; Brian Young; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2011)

A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking. - Wenjing Yin; Rajesh Inti; Amr Elshazly; Brian Young; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2011)

A 1.5GHz 890μW digital MDLL with 400fsrms integrated jitter, -55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC. - Amr Elshazly; Rajesh Inti; Brian Young; Pavan Kumar Hanumolu (ISSCC, 2012)

A 13b 315fsrms 2mW 500MS/s 1MHz bandwidth highly digital time-to-digital converter using switched ring oscillators. - Amr Elshazly; Sachin Rao; Brian Young; Pavan Kumar Hanumolu (ISSCC, 2012)

A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer. - Karthikeyan Reddy; Sachin Rao; Rajesh Inti; Brian Young; Amr Elshazly; Mrunmay Talegaonkar; Pavan Kumar Hanumolu (ISSCC, 2012)

Quality Metric for Parasternal Long Axis B-Mode Echocardiograms. - Sri-Kaushik Pavani; Navneeth Subramanian; Mithun Das Gupta; Pavan Annangi; Satish C. Govind; Brian Young (MICCAI (2), 2012)

A 16-mW 78-dB SNDR 10-MHz BW CT Delta Sigma ADC Using Residue-Cancelling VCO-Based Quantizer. - Karthikeyan Reddy; Sachin Rao; Rajesh Inti; Brian Young; Amr Elshazly; Mrunmay Talegaonkar; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2012)

Automated posteriorwall thickness measurement from B-mode ultrasound. - Pavan Annangi; Navneeth Subramanian; Satish C. Govind; Gokul Swamy; Brian Young (ISBI, 2013)

A 2.5GHz 2.2mW/25µW on/off-state power 2psrms-long-term-jitter digital clock multiplier with 3-reference-cycles power-on time. - Tejasvi Anand; Mrunmay Talegaonkar; Amr Elshazly; Brian Young; Pavan Kumar Hanumolu (ISSCC, 2013)

Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops. - Amr Elshazly; Rajesh Inti; Brian Young; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2013)

A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter. - Mrunmay Talegaonkar; Tejasvi Anand; Ahmed Elkholy; Amr Elshazly; Romesh Kumar Nandwana; Saurabh Saxena; Brian Young; Woo-Seok Choi; Pavan Kumar Hanumolu (VLSIC, 2014)

A 75dB DR 50MHz BW 3rd order CT-ΔΣ modulator using VCO-based integrators. - Brian Young; Karthik Reddy; Sachin Rao; Amr Elshazly; Tejasvi Anand; Pavan Kumar Hanumolu (VLSIC, 2014)

A 5 Gb/s, 10 ns Power-On-Time, 36 µW Off-State Power, Fast Power-On Transmitter for Energy Proportional Links. - Tejasvi Anand; Amr Elshazly; Mrunmay Talegaonkar; Brian Young; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2014)

A Noise-Shaping Time-to-Digital Converter Using Switched-Ring Oscillators - Analysis, Design, and Measurement Techniques. - Amr Elshazly; Sachin Rao; Brian Young; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2014)

A Deterministic Digital Background Calibration Technique for VCO-Based ADCs. - Sachin Rao; Karthikeyan Reddy; Brian Young; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2014)

A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop. - Guanghua Shu; Saurabh Saxena; Woo-Seok Choi; Mrunmay Talegaonkar; Rajesh Inti; Amr Elshazly; Brian Young; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2014)

A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS. - Karthikeyan Reddy; Siladitya Dey 002; Sachin Rao; Brian Young; Praveen Prabha; Pavan Kumar Hanumolu (VLSIC, 2015)

A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS. - Mrunmay Talegaonkar; Tejasvi Anand; Ahmed Elkholy; Amr Elshazly; Romesh Kumar Nandwana; Saurabh Saxena; Brian Young; Woo-Seok Choi; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2017)