SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS. - Brian Zimmer; Seng Oon Toh; Huy Vo; Yunsup Lee; Olivier Thomas; Krste Asanovic; Borivoje Nikolic (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Joint impact of random variations and RTN on dynamic writeability in 28nm bulk and FDSOI SRAM. - Brian Zimmer; Olivier Thomas; Seng Oon Toh; Taylor Vincent; Krste Asanovic; Borivoje Nikolic (ESSDERC, 2014)

Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking. - Yunsup Lee; Brian Zimmer; Andrew Waterman; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Ben Keller; Stevo Bailey; Milovan Blagojevic; Pi-Feng Chiu; Henry Cook; Rimas Avizienis; et al. (Hot Chips Symposium, 2015)

A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI. - Brian Zimmer; Yunsup Lee; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Ben Keller; Stevo Bailey; Milovan Blagojevic; Pi-Feng Chiu; Hanh-Phuc Le; Po-Hung Chen; Nicholas Sutardja; et al. (VLSIC, 2015)

Resilient Design Techniques for Improving Cache Energy Efficiency. - Brian Zimmer (2015)

A double-tail sense amplifier for low-voltage SRAM in 28nm technology. - Pi-Feng Chiu; Brian Zimmer; Borivoje Nikolic (A-SSCC, 2016)

On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoC. - Martin Cochet; Alberto Puggelli; Ben Keller; Brian Zimmer; Milovan Blagojevic; Sylvain Clerc; Philippe Roche; Jean-Luc Autran; Borivoje Nikolic (A-SSCC, 2016)

Reprogrammable redundancy for cache Vmin reduction in a 28nm RISC-V processor. - Brian Zimmer; Pi-Feng Chiu; Borivoje Nikolic; Krste Asanovic (A-SSCC, 2016)

Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC. - Ben Keller; Martin Cochet; Brian Zimmer; Yunsup Lee; Milovan Blagojevic; Jaehwa Kwak; Alberto Puggelli; Stevo Bailey; Pi-Feng Chiu; Daniel Palmer Dabbelt; Colin Schmidt 001; Elad Alon; et al. (ESSCIRC, 2016)

Strober: Fast and Accurate Sample-Based Energy Simulation for Arbitrary RTL. - Donggyu Kim; Adam M. Izraelevitz; Christopher Celio; Hokeun Kim; Brian Zimmer; Yunsup Lee; Jonathan Bachrach; Krste Asanovic (ISCA, 2016)

A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation. - Mahmut E. Sinangil; John W. Poulton; Matthew R. Fojtik; Thomas H. Greer; Stephen G. Tell; Andreas J. Gotterba; Jesse Wang; Jason Golbus; Brian Zimmer; William J. Dally; C. Thomas Gray (IEEE J. Solid State Circuits, 2016)

A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI. - Brian Zimmer; Yunsup Lee; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Ben Keller; Steven Bailey; Milovan Blagojevic; Pi-Feng Chiu; Hanh-Phuc Le; Po-Hung Chen; Nicholas Sutardja; et al. (IEEE J. Solid State Circuits, 2016)

An Agile Approach to Building RISC-V Microprocessors. - Yunsup Lee; Andrew Waterman; Henry Cook; Brian Zimmer; Ben Keller; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Stevo Bailey; Milovan Blagojevic; Pi-Feng Chiu; Rimas Avizienis; et al. (IEEE Micro, 2016)

A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI. - Ben Keller; Martin Cochet; Brian Zimmer; Jaehwa Kwak; Alberto Puggelli; Yunsup Lee; Milovan Blagojevic; Stevo Bailey; Pi-Feng Chiu; Daniel Palmer Dabbelt; Colin Schmidt 001; Elad Alon; et al. (IEEE J. Solid State Circuits, 2017)

Reprogrammable Redundancy for SRAM-Based Cache Vmin Reduction in a 28-nm RISC-V Processor. - Brian Zimmer; Pi-Feng Chiu; Borivoje Nikolic; Krste Asanovic (IEEE J. Solid State Circuits, 2017)

Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects. - Walker J. Turner; John W. Poulton; John M. Wilson 002; Xi Chen 033; Stephen G. Tell; Matthew Fojtik; Thomas H. Greer; Brian Zimmer; Sanquan Song; Nikola Nedovic; Sudhir S. Kudva; Sunil R. Sudhakaran; et al. (CICC, 2018)

A modular digital VLSI flow for high-productivity SoC design. - Brucek Khailany; Evgeni Khmer; Rangharajan Venkatesan; Jason Clemons; Joel S. Emer; Matthew Fojtik; Alicia Klinefelter; Michael Pellauer; Nathaniel Ross Pinckney; Yakun Sophia Shao; Shreesha Srinath; Christopher Torng; et al. (DAC, 2018)

A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator. - John M. Wilson 002; Walker J. Turner; John W. Poulton; Brian Zimmer; Xi Chen 033; Sudhir S. Kudva; Sanquan Song; Stephen G. Tell; Nikola Nedovic; Wenxu Zhao; Sunil R. Sudhakaran; C. Thomas Gray; et al. (ISSCC, 2018)

SwapCodes: Error Codes for Hardware-Software Cooperative GPU Pipeline Error Detection. - Michael B. Sullivan 001; Siva Kumar Sastry Hari; Brian Zimmer; Timothy Tsai 002; Stephen W. Keckler (MICRO, 2018)

A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET. - Matthew Fojtik; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Stephen G. Tell; Brian Zimmer; Tezaswi Raja; Kevin Zhou; William J. Dally; Brucek Khailany (ASYNC, 2019)

Voltage-Follower Coupling Quadrature Oscillator with Embedded Phase-Interpolator in 16nm FinFET. - Xi Chen 033; Sanquan Song; John Poulton; Nikola Nedovic; Brian Zimmer; Stephen G. Tell; C. Thomas Gray (CICC, 2019)

A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET. - Sanquan Song; John Poulton; Xi Chen 033; Brian Zimmer; Stephen G. Tell; Walker J. Turner; Sudhir S. Kudva; Nikola Nedovic; John M. Wilson 002; C. Thomas Gray; William J. Dally (CICC, 2019)

Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference. - Angad S. Rekhi; Brian Zimmer; Nikola Nedovic; Ningxi Liu; Rangharajan Venkatesan; Miaorong Wang; Brucek Khailany; William J. Dally; C. Thomas Gray (DAC, 2019)

A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology. - Rangharajan Venkatesan; Yakun Sophia Shao; Brian Zimmer; Jason Clemons; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (Hot Chips Symposium, 2019)

MAGNet: A Modular Accelerator Generator for Neural Networks. - Rangharajan Venkatesan; Yakun Sophia Shao; Miaorong Wang; Jason Clemons; Steve Dai; Matthew Fojtik; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Yanqing Zhang 002; Brian Zimmer; et al. (ICCAD, 2019)

Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture. - Yakun Sophia Shao; Jason Clemons; Rangharajan Venkatesan; Brian Zimmer; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (MICRO, 2019)

A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm. - Brian Zimmer; Rangharajan Venkatesan; Yakun Sophia Shao; Jason Clemons; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (VLSI Circuits, 2019)

A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator. - John W. Poulton; John M. Wilson 002; Walker J. Turner; Brian Zimmer; Xi Chen 033; Sudhir S. Kudva; Sanquan Song; Stephen G. Tell; Nikola Nedovic; Wenxu Zhao; Sunil R. Sudhakaran; C. Thomas Gray; et al. (IEEE J. Solid State Circuits, 2019)

6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links. - Xi Chen 033; Nikola Nedovic; Stephen G. Tell; Sudhir S. Kudva; Brian Zimmer; Thomas H. Greer; John W. Poulton; Sanquan Song; Walker J. Turner; John M. Wilson 002; C. Thomas Gray (ISSCC, 2020)

A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm. - Brian Zimmer; Rangharajan Venkatesan; Yakun Sophia Shao; Jason Clemons; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (IEEE J. Solid State Circuits, 2020)

VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference. - Steve Dai; Rangharajan Venkatesan; Mark Ren; Brian Zimmer; William J. Dally; Brucek Khailany (MLSys, 2021)

Simba: scaling deep-learning inference with chiplet-based architecture. - Yakun Sophia Shao; Jason Clemons; Rangharajan Venkatesan; Brian Zimmer; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (Commun. ACM, 2021)

VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference. - Steve Dai; Rangharajan Venkatesan; Haoxing Ren; Brian Zimmer; William J. Dally; Brucek Khailany (CoRR, 2021)

Optimal Clipping and Magnitude-aware Differentiation for Improved Quantization-aware Training. - Charbel Sakr; Steve Dai; Rangharajan Venkatesan; Brian Zimmer; William J. Dally; Brucek Khailany (ICML, 2022)

AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies. - Hao Chen 059; Walker J. Turner; Sanquan Song; Keren Zhu 001; George F. Kokai; Brian Zimmer; C. Thomas Gray; Brucek Khailany; David Z. Pan; Haoxing Ren (ISPD, 2022)

A 17-95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm. - Ben Keller; Rangharajan Venkatesan; Steve Dai; Stephen G. Tell; Brian Zimmer; William J. Dally; C. Thomas Gray; Brucek Khailany (VLSI Technology and Circuits, 2022)

A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS. - Yoshinori Nishi; John W. Poulton; Xi Chen 033; Sanquan Song; Brian Zimmer; Walker J. Turner; Stephen G. Tell; Nikola Nedovic; John M. Wilson 002; William J. Dally; C. Thomas Gray (VLSI Technology and Circuits, 2022)

An FLL-Based Clock Glitch Detector for Security Circuits in a 5nm FINFET Process. - Sanquan Song; Stephen G. Tell; Brian Zimmer; Sudhir S. Kudva; Nikola Nedovic; C. Thomas Gray (VLSI Technology and Circuits, 2022)

LNS-Madam: Low-Precision Training in Logarithmic Number System Using Multiplicative Weight Update. - Jiawei Zhao; Steve Dai; Rangharajan Venkatesan; Brian Zimmer; Mustafa Fayez Ali; Ming-Yu Liu 001; Brucek Khailany; William J. Dally; Anima Anandkumar (IEEE Trans. Computers, 2022)

A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm. - Ben Keller; Rangharajan Venkatesan; Steve Dai; Stephen G. Tell; Brian Zimmer; Charbel Sakr; William J. Dally; C. Thomas Gray; Brucek Khailany (IEEE J. Solid State Circuits, 2023)

A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS. - Yoshinori Nishi; John W. Poulton; Walker J. Turner; Xi Chen 033; Sanquan Song; Brian Zimmer; Stephen G. Tell; Nikola Nedovic; John M. Wilson 002; William J. Dally; C. Thomas Gray (IEEE J. Solid State Circuits, 2023)

Leveraging Micro-Bump Pitch Scaling to Accelerate Interposer Link Bandwidths for Future High-Performance Compute Applications. - Walker J. Turner; John W. Poulton; Yoshinori Nishi; Xi Chen 033; Brian Zimmer; Sanquan Song; John M. Wilson 002; William J. Dally; C. Thomas Gray (CICC, 2024)

16.4 High-Density and Low-Power PUF Designs in 5nm Achieving 23× and 39× BER Reduction After Unstable Bit Detection and Masking. - Sudhir S. Kudva; Mahmut Ersin Sinangil; Stephen G. Tell; Nikola Nedovic; Sanquan Song; Brian Zimmer; C. Thomas Gray (ISSCC, 2024)

A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS. - Yoshinori Nishi; John W. Poulton; Walker J. Turner; Xi Chen 033; Sanquan Song; Brian Zimmer; Stephen G. Tell; Nikola Nedovic; John M. Wilson 002; William J. Dally; C. Thomas Gray (IEEE J. Solid State Circuits, 2024)

17.6 A 100MHz Self-Calibrating RC Oscillator Capable of Clock-Glitch Detection for Hardware Security in a 3nm FinFET Process. - Nandish Mehta; Stephen G. Tell; Sanquan Song; Sudhir S. Kudva; Brian Zimmer; Mahmut E. Sinangil; C. Thomas Gray (ISSCC, 2025)