Design Automation of Test for the EX/9000TM Series Processors. - Brion L. Keller; David A. Haynes (ICCD, 1991)

The Compiled Logic Simulator. - Brion L. Keller; David P. Carlson; William Maloney (IEEE Des. Test Comput., 1991)

Delay Test: The Next Frontier for LSSD Test Systems. - Bernd Könemann; J. Barlow; Paul Chang; R. Gabrielson; C. Goertz; Brion L. Keller; Kevin McCauley; J. Tischer; Vijay S. Iyengar; Barry K. Rosen; T. Williams (ITC, 1992)

Test methodologies and design automation for IBM ASICs. - Pamela S. Gillis; Tom S. Guzowski; Brion L. Keller; Randal H. Kerr (IBM J. Res. Dev., 1996)

ATPG in practical and non-traditional applications. - Brion L. Keller; Kevin McCauley; Joseph Swenton; James Youngs (ITC, 1998)

Design and Implementation of a Parallel Weighted Random Pattern and Logic Built in Self Test Algorithm. - Paul Chang; Brion L. Keller; Sarala Paliwal (ICCD, 1999)

Using STIL to describe embedded core test requirements. - Brion L. Keller (ITC, 1999)

Effective parallel processing techniques for the generation of test data for a logic built-in self test system. - Paul Chang; Brion L. Keller; Sarala Paliwal (Asian Test Symposium, 2000)

Design and implementation of a parallel automatic test pattern generation algorithm with low test vector count. - Robert Butler; Brion L. Keller; Sarala Paliwal; Richard Schoonover; Joseph Swenton (ITC, 2000)

A SmartBIST Variant with Guaranteed Encoding. - Bernd Könemann; Carl Barnhart; Brion L. Keller; Thomas J. Snethen; Owen Farnsworth; Donald L. Wheater (Asian Test Symposium, 2001)

High Performance Parallel Fault Simulation. - Amit K. Varshney; Bapiraju Vinnakota; Eric Skuldt; Brion L. Keller (ICCD, 2001)

OPMISR: the foundation for compressed ATPG vectors. - Carl Barnhart; Vanessa Brunkhorst; Frank Distler; Owen Farnsworth; Brion L. Keller; Bernd Könemann; Andrej Ferko (ITC, 2001)

CTL the language for describing core-based test. - Rohit Kapur; Maurice Lousberg; Tony Taylor; Brion L. Keller; Paul Reuter; Douglas Kay (ITC, 2001)

Extending OPMISR beyond 10x Scan Test Efficiency. - Carl Barnhart; Vanessa Brunkhorst; Frank Distler; Owen Farnsworth; Andrew Ferko; Brion L. Keller; David Scott; Bernd Könemann; Takeshi Onodera (IEEE Des. Test Comput., 2002)

Channel Masking Synthesis for Efficient On-Chip Test Compression. - Vivek Chickermane; Brian Foutz; Brion L. Keller (ITC, 2004)

An Economic Analysis and ROI Model for Nanometer Test. - Brion L. Keller; Mick Tegethoff; Thomas Bartenstein; Vivek Chickermane (ITC, 2004)

Practical Aspects of Delay Testing for Nanometer Chips. - Vivek Chickermane; Brion L. Keller; Kevin McCauley; Anis Uzzaman (Asian Test Symposium, 2005)

Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression. - Hiroyuki Nakamura; Akio Shirokane; Yoshihito Nishizaki; Anis Uzzaman; Vivek Chickermane; Brion L. Keller; Tsutomu Ube; Yoshihiko Terauchi (Asian Test Symposium, 2005)

Encounter test OPMISR+ on-chip compression. - Brion L. Keller (ITC, 2005)

Use of MISRs for compression and diagnostics. - Brion L. Keller; Thomas Bartenstein (ITC, 2005)

A Scalable Architecture for On-Chip Compression: Options and Trade-Offs. - Anis Uzzaman; Brion L. Keller; Vivek Chickermane (ATS, 2006)

OCI: Open Compression Interface. - Bruce Cory; Rohit Kapur; Mick Tegethoff; Mark Kassab; Brion L. Keller; Kee Sup Kim; Dwayne Burek; Steven F. Oakland; Benoit Nadeau-Dostie (ITC, 2006)

A Review of Power Strategies for DFT and ATPG. - Brion L. Keller; Tom Jackson; Anis Uzzaman (ATS, 2007)

Using Programmable On-Product Clock Generation (OPCG) for Delay Test. - Brion L. Keller; Anis Uzzaman; Bibo Li; Thomas J. Snethen (ATS, 2007)

Automated handling of programmable on-product clock generation (OPCG) circuitry for delay test vector generation. - Anis Uzzaman; Bibo Li; Thomas J. Snethen; Brion L. Keller; Gary Grise (ITC, 2007)

Test Generation for State Retention Logic. - Krishna Chakravadhanula; Vivek Chickermane; Brion L. Keller; Patrick R. Gallagher Jr.; Steven Gregor (ATS, 2008)

Optimizing Test Data Volume Using Hybrid Compression. - Brion L. Keller; Sandeep Bhatia; Thomas Bartenstein; Brian Foutz; Anis Uzzaman (ATS, 2008)

Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs?. - Krishna Chakravadhanula; Vivek Chickermane; Brion L. Keller; Patrick R. Gallagher Jr.; Anis Uzzaman (Asian Test Symposium, 2009)

A Partially-Exhaustive Gate Transition Fault Model. - Brion L. Keller; Dale Meehl; Anis Uzzaman; Richard Billings (Asian Test Symposium, 2009)

Capture power reduction using clock gating aware test generation. - Krishna Chakravadhanula; Vivek Chickermane; Brion L. Keller; Patrick R. Gallagher Jr.; Prashant Narang (ITC, 2009)

CTL and Its Usage in the EDA Industry. - Rohit Kapur; Paul Reuter; Sandeep Bhatia; Brion L. Keller (IEEE Des. Test Comput., 2009)

Automatic Handling of Programmable On-Product Clock Generation (OPCG) Circuitry for Low Power Aware Delay Test. - Anis Uzzaman; Brion L. Keller; Thomas J. Snethen; Kazuhiko Iwasaki; Masayuki Arai (J. Low Power Electron., 2009)

Low cost at-speed testing using On-Product Clock Generation compatible with test compression. - Brion L. Keller; Krishna Chakravadhanula; Brian Foutz; Vivek Chickermane; R. Malneedi; Thomas J. Snethen; Vikram Iyengar; David E. Lackey; Gary Grise (ITC, 2010)

Reduction of Test Data Volume and Improvement of Diagnosability Using Hybrid Compression. - Anis Uzzaman; Brion L. Keller; Brian Foutz; Sandeep Bhatia; Thomas Bartenstein; Masayuki Arai; Kazuhiko Iwasaki (IEICE Trans. Inf. Syst., 2010)

Automation of 3D-DfT Insertion. - Sergej Deutsch; Vivek Chickermane; Brion L. Keller; Subhasish Mukherjee; Mario Konijnenburg; Erik Jan Marinissen; Sandeep Kumar Goel (Asian Test Symposium, 2011)

DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks. - Sergej Deutsch; Brion L. Keller; Vivek Chickermane; Subhasish Mukherjee; Navdeep Sood; Sandeep Kumar Goel; Ji-Jan Chen; Ashok Mehta; Frank Lee 004; Erik Jan Marinissen (ITC, 2012)

Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers. - Christos Papameletis; Brion L. Keller; Vivek Chickermane; Erik Jan Marinissen; Said Hamdioui (ETS, 2013)

Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study. - Sandeep Kumar Goel; Saman Adham; Min-Jer Wang; Ji-Jan Chen; Tze-Chiang Huang; Ashok Mehta; Frank Lee 004; Vivek Chickermane; Brion L. Keller; Thomas Valind; Subhasish Mukherjee; Navdeep Sood; et al. (ITC, 2013)

Efficient testing of hierarchical core-based SOCs. - Brion L. Keller; Krishna Chakravadhanula; Brian Foutz; Vivek Chickermane; Akhil Garg 001; Richard Schoonover; James Sage; Don Pearl; Thomas J. Snethen (ITC, 2014)

At-Speed Testing of Inter-Die Connections of 3D-SICs in the Presence of Shore Logic. - Konstantin Shibin; Vivek Chickermane; Brion L. Keller; Christos Papameletis; Erik Jan Marinissen (ATS, 2015)

A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers. - Christos Papameletis; Brion L. Keller; Vivek Chickermane; Said Hamdioui; Erik Jan Marinissen (IEEE Des. Test, 2015)