Reconfigurable RNS FIR Filter Using Higher Radix Multiplier. - J. Britto Pari; S. P. Joy Vasantha Rani (ACITY (3), 2012)

Performance Analysis of 8-Point Approximate DCT Architecture Using Conventional and Hybrid Adders. - D. Vaithiyanathan 001; Rajhans Kolhe; Alok Kumar Mishra 001; Britto Pari James; K. Kunaraj (iSES, 2020)

High Performance FPGA Implementation of Single MAC Adaptive Filter for Independent Component Analysis. - M. R. Ezilarasan; J. Britto Pari; Man-Fai Leung (J. Circuits Syst. Comput., 2023)

High speed and area efficient coded input BCSM shared LUT-based FIR filter architecture. - S. C. Prasanna; Britto Pari James; Vaithiyanathan Dhandapani (Int. J. Syst. Assur. Eng. Manag., 2024)

An Efficient FPGA-Based Welch Power Spectral Density for Real-Time Applications. - Suma Nair; Britto Pari James (J. Circuits Syst. Comput., 2025)

An area efficient FPGA design for EEG signal denoising using LMS adaptive filtering and Teager-Kaiser energy operator. - Suma Nair; Britto Pari James (Signal Image Video Process., 2025)