A monolithic 2-b delta-sigma A/D converter. - Bruce Del Signore; Donald A. Kerth; Navdeep S. Sooch; Eric J. Swanson (IEEE J. Solid State Circuits, 1990)

A 2.5-Gb/s Multi-Rate 0.25-$ mu$m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition. - Michael H. Perrott; Yunteng Huang; Rex T. Baird; Bruno W. Garlepp; Douglas Pastorello; Eric T. King; Qicheng Yu; Dan B. Kasha; Philip Steiner; Ligang Zhang; Jerrell P. Hein; Bruce Del Signore (IEEE J. Solid State Circuits, 2006)