Detection of coupling faults in RAMs. - Janusz A. Brzozowski; Bruce F. Cockburn (J. Electron. Test., 1990)

Switch-level testability of the dynamic CMOS PLA. - Bruce F. Cockburn; Janusz A. Brzozowski (Integr., 1990)

Near-optimal tests for classes of write-triggered coupling faults in RAMs. - Bruce F. Cockburn; Janusz A. Brzozowski (J. Electron. Test., 1992)

Deterministic tests for detecting singleV-coupling faults in RAMs. - Bruce F. Cockburn (J. Electron. Test., 1994)

Tutorial on semiconductor memory testing. - Bruce F. Cockburn (J. Electron. Test., 1994)

Synthesized Transparent BIST for Detecting Scrambled Pattern-Sensitive Faults in RAMs. - Bruce F. Cockburn; Y.-F. Nicole Sat (ITC, 1995)

Transition Maximization Techniques for Enhancing the Two-Pattern Fault Coverage of Pseudorandom Test Pattern Generators. - Bruce F. Cockburn; Albert L.-C. Kwong (VTS, 1998)

Cost Models for Large File Memory DRAMs with ECC and Bad Block Marking. - C. Wickman; Duncan G. Elliott; Bruce F. Cockburn (DFT, 1999)

A Comparative Simulation Study of Four Multilevel DRAMs. - Gershom Birk; Duncan G. Elliott; Bruce F. Cockburn (MTDT, 1999)

Guest Editors' Introduction: DRAM Architecture and Testing. - Bruce F. Cockburn; Fabrizio Lombardi; Fred J. Meyer (IEEE Des. Test Comput., 1999)

Fault Models and Tests for a 2-Bit-per-Cell MLDRAM. - Michael Redeker; Bruce F. Cockburn; Duncan G. Elliott (IEEE Des. Test Comput., 1999)

Voiceband signal classification using statistically optimal combinations of low-complexity discriminant variables. - Jeremy S. Sewall; Bruce F. Cockburn (IEEE Trans. Commun., 1999)

Design of an Embedded Fully-Depleted SOI SRAM. - Raymond J. Sung; John C. Koob; Tyler L. Brandon; Duncan G. Elliott; Bruce F. Cockburn (MTDT, 2001)

Panel on Advanced Embedded Memory Technologies. - Bruce F. Cockburn (MTDT, 2002)

An Investigation into Crosstalk Noise in DRAM Structures. - Michael Redeker; Bruce F. Cockburn; Duncan G. Elliott (MTDT, 2002)

Fault Modeling and Pattern-Sensitivity Testing for a Multilevel DRAM. - Michael Redeker; Bruce F. Cockburn; Duncan G. Elliott; Yunan Xiang; Sue Ann Ung (MTDT, 2002)

An Efficient Functional Test for the Massively-Parallel C ?RAM Logic-Enhanced Memory Architecture. - Xiaoling Sun; Bruce F. Cockburn; Duncan G. Elliott (DFT, 2003)

The Emergence of High-Density Semiconductor-Compatible Spintronic Memory. - Bruce F. Cockburn (ICMENS, 2003)

A Multilevel DRAM with Hierarchical Bitlines and Serial Sensing. - Bruce F. Cockburn; Jesús Hernández Tapia; Duncan G. Elliott (MTDT, 2003)

An Electrical Simulation Model for the Chalcogenide Phase-Change Memory Cell. - Daniel Salamon; Bruce F. Cockburn (MTDT, 2003)

Tutorial on Magnetic Tunnel Junction Magnetoresistive Random-Access Memory. - Bruce F. Cockburn (MTDT, 2004)

Efficient architectures for 1-D and 2-D lifting-based wavelet transforms. - Hongyu Liao; Mrinal Kr. Mandal; Bruce F. Cockburn (IEEE Trans. Signal Process., 2004)

An investigation into three-level ferroelectric memory. - Kamlesh R. Raiter; Bruce F. Cockburn (MTDT, 2005)

Test and Characterization of a Variable-Capacity Multilevel DRAM. - John C. Koob; Sue Ann Ung; Ashwin S. Rao; Daniel A. Leder; Craig S. Joly; Kristopher C. Breen; Tyler L. Brandon; Michael Hume; Bruce F. Cockburn; Duncan G. Elliott (VTS, 2005)

Design of a 3-D fully depleted SOI computational RAM. - John C. Koob; Daniel A. Leder; Raymond J. Sung; Tyler L. Brandon; Duncan G. Elliott; Bruce F. Cockburn; Lisa G. McIlrath (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Design and Characterization of a Digital Delay Locked Loop Synthesized from Black Box Standard Cells. - Bruce F. Cockburn; Keith Boyle (CCECE, 2006)

A Reconfigurable SOS-based Rayleigh Fading Channel Simulator. - Amirhossein Alimohammad 001; Bruce F. Cockburn (SiPS, 2006)

On the Effects of Colored Noise on the Performance of LDPC Codes. - Saeed Sharifi Tehrani; Bruce F. Cockburn; Stephen Bates (SiPS, 2006)

Using Stacked Bitlines and Hybrid ROM Cells to Form ROM and SRAM-ROM With Increased Storage Density. - Tyler L. Brandon; Duncan G. Elliott; Bruce F. Cockburn (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

An Efficient Parallel Architecture for Implementing LST Decoding in MIMO Systems. - Amirhossein Alimohammad 001; Bruce F. Cockburn (IEEE Trans. Signal Process., 2006)

A Compact Fading Channel Simulator Using Timing-Driven Resource Sharing. - Amirhossein Alimohammad 001; Saeed Fouladi Fard; Bruce F. Cockburn; Christian Schlegel (ASAP, 2007)

A Flexible Filter Processor for Fading Channel Simulation. - Amirhossein Alimohammad 001; Saeed Fouladi Fard; Bruce F. Cockburn; Christian Schlegel (FCCM, 2007)

Compound Uniform Random Number Generators with On-Chhip Correlation and Distribution Measurements. - Amirhossein Alimohammad 001; Saeed Fouladi Fard; Bruce F. Cockburn; Christian Schlegel (FPT, 2007)

An Improved SOS-Based Fading Channel Emulator. - Amirhossein Alimohammad 001; Saeed Fouladi Fard; Bruce F. Cockburn; Christian Schlegel (VTC Fall, 2007)

Efficient allocation of packet-level forward error correction in video streaming over the Internet. - Yufei Yuan; Bruce F. Cockburn; Thomas Sikora; Mrinal K. Mandal 001 (J. Electronic Imaging, 2007)

Design and Test of a 175-Mb/s, Rate-1/2 (128, 3, 6) Low-Density Parity-Check Convolutional Code Encoder and Decoder. - Ramkrishna Swamy; Stephen Bates; Tyler L. Brandon; Bruce F. Cockburn; Duncan G. Elliott; John C. Koob; Zhengang Chen (IEEE J. Solid State Circuits, 2007)

A Novel Technique for Efficient Hardware Simulation of Spatiotemporally Correlated MIMO Fading Channels. - Amirhossein Alimohammad 001; Saeed Fouladi Fard; Bruce F. Cockburn; Christian Schlegel (ICC, 2008)

On the efficiency and accuracy of hybrid pseudo-random number generators for FPGA-based simulations. - Amirhossein Alimohammad 001; Saeed Fouladi Fard; Bruce F. Cockburn; Christian Schlegel (IPDPS, 2008)

A single-FPGA multipath MIMO fading channel simulator. - Amirhossein Alimohammad 001; Saeed Fouladi Fard; Bruce F. Cockburn; Christian Schlegel (ISCAS, 2008)

A 600-Mb/s encoder and decoder for low-density parity-check convolutional codes. - Tyler L. Brandon; John C. Koob; Leendert van den Berg; Zhengang Chen; Amirhossein Alimohammad 001; Ramkrishna Swamy; Jason Klaus; Stephen Bates; Vincent C. Gaudet; Bruce F. Cockburn; Duncan G. Elliott (ISCAS, 2008)

Hardware-based Error Rate Testing of Digital Baseband Communication Systems. - Amirhossein Alimohammad 001; Saeed Fouladi Fard; Bruce F. Cockburn (ITC, 2008)

An Accurate and Compact Rayleigh and Rician Fading Channel Simulator. - Amirhossein Alimohammad 001; Saeed Fouladi Fard; Bruce F. Cockburn; Christian Schlegel (VTC Spring, 2008)

A scalable LDPC decoder ASIC architecture with bit-serial message exchange. - Tyler L. Brandon; Robert Hang; Gary Block; Vincent C. Gaudet; Bruce F. Cockburn; Sheryl L. Howard; Christian Giasson; Keith Boyle; Paul Goud; Siavash Sheikh Zeinoddin; Anthony Rapley; Stephen Bates; et al. (Integr., 2008)

A Compact Single-FPGA Fading-Channel Simulator. - Amirhossein Alimohammad 001; Saeed Fouladi Fard; Bruce F. Cockburn; Christian Schlegel (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Efficient Implementation of Low-Density Parity-Check Convolutional Code Encoders With Built-In Termination. - Zhengang Chen; Tyler L. Brandon; Stephen Bates; Duncan G. Elliott; Bruce F. Cockburn (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

A Compact and Accurate Gaussian Variate Generator. - Amirhossein Alimohammad 001; Saeed Fouladi Fard; Bruce F. Cockburn; Christian Schlegel (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Modeling and Hardware Implementation Aspects of Fading Channel Simulators. - Amirhossein Alimohammad 001; Bruce F. Cockburn (IEEE Trans. Veh. Technol., 2008)

FPGA-based accelerator for the verification of leading-edge wireless systems. - Amirhossein Alimohammad 001; Saeed Fouladi Fard; Bruce F. Cockburn (DAC, 2009)

A flexible layered architecture for accurate digital baseband algorithm development and verification. - Amirhossein Alimohammad 001; Saeed Fouladi Fard; Bruce F. Cockburn (DATE, 2009)

A Single FPGA Filter-Based Multipath Fading Emulator. - Saeed Fouladi Fard; Amirhossein Alimohammad 001; Bruce F. Cockburn; Christian Schlegel (GLOBECOM, 2009)

A versatile fading simulator for on-chip verification of MIMO communication systems. - Saeed Fouladi Fard; Amirhossein Alimohammad 001; Bruce F. Cockburn; Christian Schlegel (SoCC, 2009)

High path-count multirate Rayleigh fading channel simulator with time-multiplexed datapath. - Saeed Fouladi Fard; Amirhossein Alimohammad 001; Bruce F. Cockburn; Christian Schlegel (SoCC, 2009)

Compact Rayleigh and Rician fading simulator based on random walk processes. - Amirhossein Alimohammad 001; Saeed Fouladi Fard; Bruce F. Cockburn; Christian Schlegel (IET Commun., 2009)

A Compact 1.1-Gb/s Encoder and a Memory-Based 600-Mb/s Decoder for LDPC Convolutional Codes. - Tyler L. Brandon; John C. Koob; Leendert van den Berg; Zhengang Chen; Amirhossein Alimohammad 001; Ramkrishna Swamy; Jason Klaus; Stephen Bates; Vincent C. Gaudet; Bruce F. Cockburn; Duncan G. Elliott (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Near-optimal and efficient MIMO detectors for 64-QAM symbols. - Arsene Pankeu Yomi; Bruce F. Cockburn (CCECE, 2010)

A Unified Architecture for the Accurate and High-Throughput Implementation of Six Key Elementary Functions. - Amirhossein Alimohammad 001; Saeed Fouladi Fard; Bruce F. Cockburn (IEEE Trans. Computers, 2010)

Jointly Designed Architecture-Aware LDPC Convolutional Codes and High-Throughput Parallel Encoders/Decoders. - Zhengang Chen; Tyler L. Brandon; Duncan G. Elliott; Stephen Bates; Witold A. Krzymien; Bruce F. Cockburn (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

An FPGA-Based Simulator for High Path Count Rayleigh and Rician Fading. - Saeed Fouladi Fard; Amirhossein Alimohammad 001; Bruce F. Cockburn (IEEE Trans. Veh. Technol., 2010)

Accurate multiple-input multiple-output fading channel simulator using a compact and highthroughput reconfigurable architecture. - Amirhossein Alimohammad 001; Saeed Fouladi Fard; Bruce F. Cockburn (IET Commun., 2011)

Single-field programmable gate array simulator for geometric multiple-input multiple-output fading channel models. - Saeed Fouladi Fard; Amirhossein Alimohammad 001; Bruce F. Cockburn (IET Commun., 2011)

Hardware Implementation of Rayleigh and Ricean Variate Generators. - Amirhossein Alimohammad 001; Saeed Fouladi Fard; Bruce F. Cockburn (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Design and Characterization of a Multilevel DRAM. - John C. Koob; Sue Ann Ung; Bruce F. Cockburn; Duncan G. Elliott (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Low power asynchronous packet-based baseband transceiver for wireless sensor networks. - Malihe Ahmadi; Bruce F. Cockburn; Christian Schlegel (MWSCAS, 2012)

Accurate simulation of non-isotropic fading channels with arbitrary temporal correlation. - Amirhossein Alimohammad 001; Saeed Fouladi Fard; Bruce F. Cockburn (IET Commun., 2012)

Layered space-time multiple-input multiple-output detector with parameterisable performance. - Amirhossein Alimohammad 001; Santosh V. Nagaraj; Saeed Fouladi Fard; Bruce F. Cockburn (IET Commun., 2012)

Hardware Implementation of Nakagami and Weibull Variate Generators. - Amirhossein Alimohammad 001; Saeed Fouladi Fard; Bruce F. Cockburn (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Reconfigurable performance measurement system-on-a-chip for baseband wireless algorithm design and verification. - Amirhossein Alimohammad 001; Saeed Fouladi Fard; Bruce F. Cockburn (IEEE Wirel. Commun., 2012)

Electromagnetic Energy and Data Transfer in Biological Tissues Using Loop Antennas. - Navid Rezaei; Deyasini Majumdar; Bruce F. Cockburn; Christian Schlegel (ANT/SEIT, 2013)

Designing Next-generation Implantable Wireless Telemetry. - Deyasini Majumdar; Christian Schlegel; Navid Rezaei; Bruce F. Cockburn (BIODEVICES, 2014)

Adaptive dual-threshold neural signal compression suitable for implantable recording. - Russell Dodd; Bruce F. Cockburn; Vincent C. Gaudet (ICASSP, 2014)

Neural Spike Compression Using Feature Extraction and a Fuzzy C-Means Codebook. - Russell Dodd; Bruce F. Cockburn; Vincent C. Gaudet (ISMVL, 2014)

Electromagnetic Energy and Data Transfer for a Neural Implant. - Navid Rezaei; Deyasini Majumdar; Bruce F. Cockburn; Christian Schlegel (J. Ubiquitous Syst. Pervasive Networks, 2014)

Stochastic circuit design and performance evaluation of vector quantization. - Ran Wang; Jie Han 001; Bruce F. Cockburn; Duncan G. Elliott (ASAP, 2015)

Minimizing the number of process corner simulations during design verification. - Michael Shoniker; Bruce F. Cockburn; Jie Han 001; Witold Pedrycz (DATE, 2015)

Design and evaluation of stochastic FIR filters. - Ran Wang; Jie Han 001; Bruce F. Cockburn; Duncan G. Elliott (PACRIM, 2015)

A novel gate grading approach for soft error tolerance in combinational circuits. - Mohammad Saeed Ansari; Ali Mahani 001; Jie Han 001; Bruce F. Cockburn (CCECE, 2016)

Implementation of decoders for symmetric low density parity check codes on parallel computation platforms using OpenCL. - Bruce F. Cockburn; Andrew J. Maier (CCECE, 2016)

SRAM memory margin probability failure estimation using Gaussian Process regression. - Manish Rana; Ramon Canal; Jie Han 001; Bruce F. Cockburn (ICCD, 2016)

Design, evaluation and fault-tolerance analysis of stochastic FIR filters. - Ran Wang; Jie Han 001; Bruce F. Cockburn; Duncan G. Elliott (Microelectron. Reliab., 2016)

Stochastic Circuit Design and Performance Evaluation of Vector Quantization for Different Error Measures. - Ran Wang; Jie Han 001; Bruce F. Cockburn; Duncan G. Elliott (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A true random number generator based on parallel STT-MTJs. - Yuanzhuo Qu; Jie Han 001; Bruce F. Cockburn; Witold Pedrycz; Yue Zhang 010; Weisheng Zhao (DATE, 2017)

Optimization of Low-Density Parity Check decoder performance for OpenCL designs synthesized to FPGAs. - Andrew J. Maier; Bruce F. Cockburn (J. Parallel Distributed Comput., 2017)

Low-Power Approximate Multipliers Using Encoded Partial Products and Approximate Compressors. - Mohammad Saeed Ansari; Honglan Jiang; Bruce F. Cockburn; Jie Han 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2018)

Automatic Selection of Process Corner Simulations for Faster Design Verification. - Michael Shoniker; Oleg Oleynikov; Bruce F. Cockburn; Jie Han 001; Manish Rana; Witold Pedrycz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Feedback-Based Low-Power Soft-Error-Tolerant Design for Dual-Modular Redundancy. - Yan Li; Yufeng Li 003; Jie Han 001; Jianhao Hu; Fan Yang 001; Xuan Zeng 001; Bruce F. Cockburn; Jie Chen 002 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Approximate Leading One Detector Design for a Hardware-Efficient Mitchell Multiplier. - Shyama Gandhi; Mohammad Saeed Ansari; Bruce F. Cockburn; Jie Han 001 (CCECE, 2019)

Design and Evaluation of an FPGA-based Hardware Accelerator for Deflate Data Decompression. - Morgan Ledwon; Bruce F. Cockburn; Jie Han 001 (CCECE, 2019)

A Hardware-Efficient Logarithmic Multiplier with Improved Accuracy. - Mohammad Saeed Ansari; Bruce F. Cockburn; Jie Han 001 (DATE, 2019)

Characterizing Approximate Adders and Multipliers Optimized under Different Design Constraints. - Honglan Jiang; Francisco J. H. Santiago; Mohammad Saeed Ansari; Leibo Liu; Bruce F. Cockburn; Fabrizio Lombardi; Jie Han 001 (ACM Great Lakes Symposium on VLSI, 2019)

High-Throughput FPGA-Based Hardware Accelerators for Deflate Compression and Decompression Using High-Level Synthesis. - Morgan Ledwon; Bruce F. Cockburn; Jie Han 001 (IEEE Access, 2020)

Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers. - Mohammad Saeed Ansari; Vojtech Mrazek; Bruce F. Cockburn; Lukás Sekanina; Zdenek Vasícek; Jie Han 001 (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A Logarithmic Floating-Point Multiplier for the Efficient Training of Neural Networks. - Zijing Niu; Honglan Jiang; Mohammad Saeed Ansari; Bruce F. Cockburn; Leibo Liu; Jie Han 001 (ACM Great Lakes Symposium on VLSI, 2021)

Fast and low-power leading-one detectors for energy-efficient logarithmic computing. - Mohammad Saeed Ansari; Shyama Gandhi; Bruce F. Cockburn; Jie Han 001 (IET Comput. Digit. Tech., 2021)

An Improved Logarithmic Multiplier for Energy-Efficient Neural Computing. - Mohammad Saeed Ansari; Bruce F. Cockburn; Jie Han 001 (IEEE Trans. Computers, 2021)

Low-Power Approximate Logarithmic Squaring Circuit Design for DSP Applications. - Mohammad Saeed Ansari; Bruce F. Cockburn; Jie Han 001 (IEEE Trans. Emerg. Top. Comput., 2022)

Hardware-Efficient Logarithmic Floating-Point Multipliers for Error-Tolerant Applications. - Zijing Niu; Tingting Zhang; Honglan Jiang; Bruce F. Cockburn; Leibo Liu; Jie Han 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)