Composing with Genetic Algorithms. - Bruce L. Jacob (ICMC, 1995)

The trading function in action. - Bruce L. Jacob; Trevor N. Mudge (ACM SIGOPS European Workshop, 1996)

An Analytical Model for Designing Memory Hierarchies. - Bruce L. Jacob; Peter M. Chen; Seth R. Silverman; Trevor N. Mudge (IEEE Trans. Computers, 1996)

Software-Managed Address Translation. - Bruce L. Jacob; Trevor N. Mudge (HPCA, 1997)

A Comment on "An Analytical Model for Designing Memory Hierarchies". - Bruce L. Jacob; Peter M. Chen; Seth R. Silverman; Trevor N. Mudge (IEEE Trans. Computers, 1997)

Software-oriented memory-management design. - Bruce L. Jacob (1997)

A Look at Several Memory Management Units, TLB-Refill Mechanisms, and Page Table Organizations. - Bruce L. Jacob; Trevor N. Mudge (ASPLOS, 1998)

Virtual Memory: Issues of Implementation. - Bruce L. Jacob; Trevor N. Mudge (Computer, 1998)

Virtual memory in contemporary microprocessors. - Bruce L. Jacob; Trevor N. Mudge (IEEE Micro, 1998)

Fifth Annual Workshop on Computer Education. - David R. Kaeli; Bruce L. Jacob (HPCA, 1999)

A Performance Comparison of Contemporary DRAM Architectures. - Vinodh Cuppu; Bruce L. Jacob; Brian Davis; Trevor N. Mudge (ISCA, 1999)

The New DRAM Interfaces: SDRAM, RDRAM and Variants. - Brian Davis; Bruce L. Jacob; Trevor N. Mudge (ISHPC, 2000)

The performance and energy consumption of three embedded real-time operating systems. - Kathleen Baynes; Chris Collins; Eric Fiterman; Brinda Ganesh; Paul Kohout; Christine Smit; Tiebing Zhang; Bruce L. Jacob (CASES, 2001)

Transparent data-memory organizations for digital signal processors. - Sadagopan Srinivasan; Vinodh Cuppu; Bruce L. Jacob (CASES, 2001)

Improving the Precise Interrupt Mechanism of Software-Managed TLB Miss Handlers. - Aamer Jaleel; Bruce L. Jacob (HiPC, 2001)

In-Line Interrupt Handling for Software-Managed TLBs. - Aamer Jaleel; Bruce L. Jacob (ICCD, 2001)

Concurrency, latency, or system overhead: which has the largest impact on uniprocessor DRAM-system performance?. - Vinodh Cuppu; Bruce L. Jacob (ISCA, 2001)

High-Performance DRAMs in Workstation Environments. - Vinodh Cuppu; Bruce L. Jacob; Brian Davis; Trevor N. Mudge (IEEE Trans. Computers, 2001)

Uniprocessor Virtual Memory without TLBs. - Bruce L. Jacob; Trevor N. Mudge (IEEE Trans. Computers, 2001)

Introduction to the two special issues on memory. - Bruce L. Jacob; Shuvra S. Bhattacharyya (ACM Trans. Embed. Comput. Syst., 2002)

A control-theoretic approach to dynamic voltage scheduling. - Ankush Varma; Brinda Ganesh; Mainak Sen; Suchismita Roy Choudhury; Lakshmi Srinivasan; Bruce L. Jacob (CASES, 2003)

Hardware support for real-time operating systems. - Paul Kohout; Brinda Ganesh; Bruce L. Jacob (CODES+ISSS, 2003)

A Case for Studying DRAM Issues at the System Level. - Bruce L. Jacob (IEEE Micro, 2003)

The Performance and Energy Consumption of Embedded Real-Time Operating Systems. - Kathleen Baynes; Chris Collins; Eric Fiterman; Brinda Ganesh; Paul Kohout; Christine Smit; Tiebing Zhang; Bruce L. Jacob (IEEE Trans. Computers, 2003)

Extended Split-Issue: Enabling Flexibility in the Hardware Implementation of NUAL VLIW DSPs. - Bharath Iyer; Sadagopan Srinivasan; Bruce L. Jacob (ISCA, 2004)

Performance characteristics of MAUI: an intelligent memory system architecture. - Justin Teller; Charles B. Silio Jr.; Bruce L. Jacob (Memory System Performance, 2005)

TERPS: the embedded reliable processing system. - Hongxia Wang; Samuel Rodríguez; Cagdas Dirik; Amol Gole; Vincent Chan; Bruce L. Jacob (ASP-DAC, 2005)

Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions. - Aamer Jaleel; Bruce L. Jacob (HPCA, 2005)

BioBench: A Benchmark Suite of Bioinformatics Applications. - Kursad Albayraktaroglu; Aamer Jaleel; Xue Wu 002; Manoj Franklin; Bruce L. Jacob; Chau-Wen Tseng; Donald Yeung (ISPASS, 2005)

DRAMsim: a memory system simulator. - David Wang 003; Brinda Ganesh; Nuengwong Tuaycharoen; Kathleen Baynes; Aamer Jaleel; Bruce L. Jacob (SIGARCH Comput. Archit. News, 2005)

Modeling heterogeneous SoCs with SystemC: a digital/MEMS case study. - Ankush Varma; Muhammad Yaqub Afridi; Akin Akturk; Paul Klein; Allen R. Hefner; Bruce L. Jacob (CASES, 2006)

Last level cache (LLC) performance of data mining workloads on a CMP - a case study of parallel bioinformatics workloads. - Aamer Jaleel; Matthew Mattina; Bruce L. Jacob (HPCA, 2006)

Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm). - Samuel Rodríguez; Bruce L. Jacob (ISLPED, 2006)

In-Line Interrupt Handling and Lock-Up Free Translation Lookaside Buffers (TLBs). - Aamer Jaleel; Bruce L. Jacob (IEEE Trans. Computers, 2006)

Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling. - Brinda Ganesh; Aamer Jaleel; David Wang 003; Bruce L. Jacob (HPCA, 2007)

Memory Systems: Cache, DRAM, Disk - Bruce L. Jacob; Spencer W. Ng; David T. Wang (Morgan Kaufmann, 2008)

Accurate and fast system-level power modeling: An XScale-based case study. - Ankush Varma; Eric Debes; Igor Kozintsev; Paul Klein; Bruce L. Jacob (ACM Trans. Embed. Comput. Syst., 2008)

The performance of PC solid-state disks (SSDs) as a function of bandwidth, concurrency, device architecture, and system organization. - Cagdas Dirik; Bruce L. Jacob (ISCA, 2009)

The Memory System: You Can't Avoid It, You Can't Ignore It, You Can't Fake It - Bruce L. Jacob (The Memory System, 2009)

Fine-Grained Activation for Power Reduction in DRAM. - Elliott Cooper-Balis; Bruce L. Jacob (IEEE Micro, 2010)

Let there be light!: the future of memory systems is photonics and 3D stacking. - Keren Bergman; Gilbert Hendry; Paul Hargrove; John Shalf; Bruce L. Jacob; K. Scott Hemmert; Arun Rodrigues; David R. Resnick (MSPC, 2011)

An analytical model to estimate PCM failure probability due to process variations. - Mu-Tien Chang; Bruce L. Jacob (SoCC, 2011)

DRAMSim2: A Cycle Accurate Memory System Simulator. - Paul Rosenfeld; Elliott Cooper-Balis; Bruce L. Jacob (IEEE Comput. Archit. Lett., 2011)

The structural simulation toolkit. - Arun F. Rodrigues; K. Scott Hemmert; Brian W. Barrett; Chad D. Kersey; Ron A. Oldfield; M. Weston; R. Risen; J. Cook; Paul Rosenfeld; E. CooperBalls; Bruce L. Jacob (SIGMETRICS Perform. Evaluation Rev., 2011)

Buffer-on-board memory systems. - Elliott Cooper-Balis; Paul Rosenfeld; Bruce L. Jacob (ISCA, 2012)

Energy-Efficient Cached DIMM Architecture. - Mu-Tien Chang; Joe Gross; Bruce L. Jacob (MASCOTS, 2012)

Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM. - Mu-Tien Chang; Paul Rosenfeld; Shih-Lien Lu; Bruce L. Jacob (HPCA, 2013)

Coordinated refresh: Energy efficient techniques for DRAM refresh scheduling. - Ishwar Bhati; Zeshan Chishti; Bruce L. Jacob (ISLPED, 2013)

High-bandwidth, high-capacity, low-power memory systems. - Bruce L. Jacob (ICSAMOS, 2014)

Flexible auto-refresh: enabling scalable and energy-efficient DRAM refresh reductions. - Ishwar Bhati; Zeshan Chishti; Shih-Lien Lu; Bruce L. Jacob (ISCA, 2015)

The Semantic Gap Between Software and the Memory System. - Jim Stevens; Paul Tschirhart; Bruce L. Jacob (MEMSYS, 2015)

Bringing Modern Hierarchical Memory Systems Into Focus: A study of architecture and workload factors on system performance. - Paul Tschirhart; Jim Stevens; Zeshan Chishti; Shih-Lien Lu; Bruce L. Jacob (MEMSYS, 2015)

Low Latency, High Bisection-Bandwidth Networks for Exascale Memory Systems. - Shang Li 001; Po-Chun Huang; David Banks; Max DePalma; Ahmed Elshaarany; K. Scott Hemmert; Arun Rodrigues; Emily Ruppel; Yitian Wang; Jim Ang; Bruce L. Jacob (MEMSYS, 2016)

Fast full system memory checkpointing with SSD-aware memory controller. - Jim Stevens; Paul Tschirhart; Bruce L. Jacob (MEMSYS, 2016)

The Case for Associative DRAM Caches. - Paul Tschirhart; Jim Stevens; Zeshan Chishti; Bruce L. Jacob (MEMSYS, 2016)

The Case for VLIW-CMP as a Building Block for Exascale. - Bruce L. Jacob (IEEE Comput. Archit. Lett., 2016)

The 2 PetaFLOP, 3 Petabyte, 9 TB/s, 90 kW Cabinet: A System Architecture for Exascale and Big Data. - Bruce L. Jacob (IEEE Comput. Archit. Lett., 2016)

DRAM Refresh Mechanisms, Penalties, and Trade-Offs. - Ishwar Bhati; Mu-Tien Chang; Zeshan Chishti; Shih-Lien Lu; Bruce L. Jacob (IEEE Trans. Computers, 2016)

Proceedings of the International Symposium on Memory Systems, MEMSYS 2017, Alexandria, VA, USA, October 02 - 05, 2017 - Bruce L. Jacob (MEMSYS, 2017)

Using run-time reverse-engineering to optimize DRAM refresh. - Deepak M. Mathew; Éder F. Zulian; Matthias Jung 001; Kira Kraft; Christian Weis; Bruce L. Jacob; Norbert Wehn (MEMSYS, 2017)

Exascale Interconnect Topology Characterization and Parameter Exploration. - Shang Li 001; Po-Chun Huang; Bruce L. Jacob (HPCC/SmartCity/DSS, 2018)

Memory-systems challenges in realizing monolithic computers. - Meenatchi Jagasivamani; Candace Walden; Devesh Singh; Luyi Kang; Shang Li 001; Mehdi Asnaashari; Sylvain Dubois; Bruce L. Jacob; Donald Yeung (MEMSYS, 2018)

A performance & power comparison of modern high-speed DRAM architectures. - Shang Li 001; Dhiraj Reddy; Bruce L. Jacob (MEMSYS, 2018)

Main memory latency simulation: the missing link. - Rommel Sánchez Verdejo; Kazi Asifuzzaman; Milan Radulovic; Petar Radojkovic; Eduard Ayguadé; Bruce L. Jacob (MEMSYS, 2018)

Design for ReRAM-based main-memory architectures. - Meenatchi Jagasivamani; Candace Walden; Devesh Singh; Luyi Kang; Shang Li 001; Mehdi Asnaashari; Sylvain Dubois; Donald Yeung; Bruce L. Jacob (MEMSYS, 2019)

Statistical DRAM modeling. - Shang Li 001; Bruce L. Jacob (MEMSYS, 2019)

Rethinking cycle accurate DRAM simulation. - Shang Li 001; Rommel Sánchez Verdejo; Petar Radojkovic; Bruce L. Jacob (MEMSYS, 2019)

Analyzing the Monolithic Integration of a ReRAM-Based Main Memory Into a CPU's Die. - Meenatchi Jagasivamani; Candace Walden; Devesh Singh; Luyi Kang; Shang Li 001; Mehdi Asnaashari; Sylvain Dubois; Bruce L. Jacob; Donald Yeung (IEEE Micro, 2019)

PROFET: Modeling System Performance and Energy Without Simulating the CPU. - Milan Radulovic; Rommel Sánchez Verdejo; Paul M. Carpenter; Petar Radojkovic; Bruce L. Jacob; Eduard Ayguadé (Proc. ACM Meas. Anal. Comput. Syst., 2019)

Tileable Monolithic ReRAM Memory Design. - Meenatchi Jagasivamani; Candace Walden; Devesh Singh; Luyi Kang; Mehdi Asnaashari; Sylvain Dubois; Bruce L. Jacob; Donald Yeung (COOL CHIPS, 2020)

DRAMsim3: A Cycle-Accurate, Thermal-Capable DRAM Simulator. - Shang Li 001; Zhiyuan Yang 001; Dhiraj Reddy; Ankur Srivastava 001; Bruce L. Jacob (IEEE Comput. Archit. Lett., 2020)

Zoned FTL: Achieve Resource Isolation via Hardware Virtualization. - Luyi Kang; Bruce L. Jacob (MEMSYS, 2021)

IceClave: A Trusted Execution Environment for In-Storage Computing. - Luyi Kang; Yuqi Xue; Weiwei Jia 001; Xiaohao Wang; Jongryool Kim; Changhwan Youn; Myeong Joon Kang; Hyung Jin Lim; Bruce L. Jacob; Jian Huang 006 (MICRO, 2021)

Monolithically Integrating Non-Volatile Main Memory over the Last-Level Cache. - Candace Walden; Devesh Singh; Meenatchi Jagasivamani; Shang Li 001; Luyi Kang; Mehdi Asnaashari; Sylvain Dubois; Bruce L. Jacob; Donald Yeung (ACM Trans. Archit. Code Optim., 2021)

Building A Trusted Execution Environment for In-Storage Computing. - Yuqi Xue; Luyi Kang; Weiwei Jia 001; Xiaohao Wang; Jongryool Kim; Changhwan Youn; Myeong Joon Kang; Hyung Jin Lim; Bruce L. Jacob; Jian Huang 006 (CoRR, 2022)