Static timing analysis for self resetting circuits. - Vinod Narayanan; Barbara A. Chappell; Bruce M. Fleischer (ICCAD, 1996)

Blue Gene: A vision for protein science using a petaflop supercomputer. - Frances E. Allen; George S. Almási; Wanda Andreoni; Daniel K. Beece; Bruce J. Berne; Arthur A. Bright; José R. Brunheroto; Calin Cascaval; José G. Castaños; Paul Coteus; Paul Crumley; Alessandro Curioni; et al. (IBM Syst. J., 2001)

The IBM eServer z990 floating-point unit. - Guenter Gerwig; Holger Wetter; Eric M. Schwarz; Juergen Haess; Christopher A. Krygowski; Bruce M. Fleischer; Michael Kroener (IBM J. Res. Dev., 2004)

4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor. - Brian W. Curran; Bradley D. McCredie; Leonid Sigal; Eric M. Schwarz; Bruce M. Fleischer; Yuen H. Chan; D. Webber; Vaden Vaden; A. Goyal (ISSCC, 2006)

64-bit prefix adders: Power-efficient topologies and design solutions. - Ching Zhou; Bruce M. Fleischer; Michael Gschwind; Ruchir Puri (CICC, 2009)

A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation. - Gary S. Ditlow; Robert K. Montoye; Salvatore N. Storino; Sherman M. Dance; Sebastian Ehrenreich; Bruce M. Fleischer; Thomas W. Fox; Kyle M. Holmes; Junichi Mihara; Yutaka Nakamura; Shohji Onishi; Robert Shearer; et al. (ISSCC, 2011)

Exponent monitoring for low-cost concurrent error detection in FPU control logic. - Michail Maniatakos; Yiorgos Makris; Prabhakar Kudva; Bruce M. Fleischer (VTS, 2011)

Low-Cost Concurrent Error Detection for Floating-Point Unit (FPU) Controllers. - Michail Maniatakos; Prabhakar Kudva; Bruce M. Fleischer; Yiorgos Makris (IEEE Trans. Computers, 2013)

Active Memory Cube: A processing-in-memory architecture for exascale systems. - Ravi Nair; Samuel Antão; Carlo Bertolli; Pradip Bose; José R. Brunheroto; Tong Chen 001; Chen-Yong Cher; Carlos H. A. Costa; J. Doi; Constantinos Evangelinos; Bruce M. Fleischer; Thomas W. Fox; et al. (IBM J. Res. Dev., 2015)

A statistical critical path monitor in 14nm CMOS. - Bruce M. Fleischer; Christos Vezyrtzis; Karthik Balakrishnan; Keith A. Jenkins (ICCD, 2016)

Synthesis design strategies for energy-efficient microprocessors. - Ching Zhou; Yu-Shiang Lin; Pong-Fei Lu; Bruce M. Fleischer; David J. Frank; Leland Chang (ICCD, 2016)

Across the Stack Opportunities for Deep Learning Acceleration. - Vijayalakshmi Srinivasan; Bruce M. Fleischer; Sunil Shukla; Matthew M. Ziegler; Joel Silberman; Jinwook Oh; Jungwook Choi; Silvia M. Mueller; Ankur Agrawal; Tina Babinsky; Nianzheng Cao; Chia-Yu Chen; et al. (ISLPED, 2018)

A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference. - Bruce M. Fleischer; Sunil Shukla; Matthew M. Ziegler; Joel Silberman; Jinwook Oh; Vijayalakshmi Srinivasan; Jungwook Choi; Silvia M. Mueller; Ankur Agrawal; Tina Babinsky; Nianzheng Cao; Chia-Yu Chen; et al. (VLSI Circuits, 2018)

DLFloat: A 16-b Floating Point Format Designed for Deep Learning Training and Inference. - Ankur Agrawal; Bruce M. Fleischer; Silvia M. Mueller; Xiao Sun 013; Naigang Wang; Jungwook Choi; Kailash Gopalakrishnan (ARITH, 2019)

A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference. - Jinwook Oh; Sae Kyu Lee; Mingu Kang; Matthew M. Ziegler; Joel Silberman; Ankur Agrawal; Swagath Venkataramani; Bruce M. Fleischer; Michael Guillorn; Jungwook Choi; Wei Wang 333; Silvia M. Mueller; et al. (VLSI Circuits, 2020)

Efficient AI System Design With Cross-Layer Approximate Computing. - Swagath Venkataramani; Xiao Sun 013; Naigang Wang; Chia-Yu Chen; Jungwook Choi; Mingu Kang; Ankur Agarwal; Jinwook Oh; Shubham Jain; Tina Babinsky; Nianzheng Cao; Thomas W. Fox; et al. (Proc. IEEE, 2020)

RaPiD: AI Accelerator for Ultra-low Precision Training and Inference. - Swagath Venkataramani; Vijayalakshmi Srinivasan; Wei Wang 333; Sanchari Sen; Jintao Zhang; Ankur Agrawal; Monodeep Kar; Shubham Jain; Alberto Mannari; Hoang Tran; Yulong Li; Eri Ogawa; et al. (ISCA, 2021)

A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling. - Ankur Agrawal; Sae Kyu Lee; Joel Silberman; Matthew M. Ziegler; Mingu Kang; Swagath Venkataramani; Nianzheng Cao; Bruce M. Fleischer; Michael Guillorn; Matt Cohen; Silvia M. Mueller; Jinwook Oh; et al. (ISSCC, 2021)

A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling. - Sae Kyu Lee; Ankur Agrawal; Joel Silberman; Matthew M. Ziegler; Mingu Kang; Swagath Venkataramani; Nianzheng Cao; Bruce M. Fleischer; Michael Guillorn; Matthew Cohen; Silvia M. Mueller; Jinwook Oh; et al. (IEEE J. Solid State Circuits, 2022)

14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC. - Monodeep Kar; Joel Silberman; Swagath Venkataramani; Viji Srinivasan; Bruce M. Fleischer; Joshua Rubin; JohnDavid Lancaster; Sae Kyu Lee; Matthew Cohen; Matthew M. Ziegler; Nianzheng Cao; Sandra Woodward; et al. (ISSCC, 2024)

Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC. - Monodeep Kar; Joel Silberman; Swagath Venkataramani; Viji Srinivasan; Bruce M. Fleischer; Joshua Rubin; JohnDavid Lancaster; Sae Kyu Lee; Matthew Cohen; Matthew M. Ziegler; Nianzheng Cao; Sandra Woodward; et al. (IEEE J. Solid State Circuits, 2025)