Accelerating Algorithms using a Dataflow Graph in a Reconfigurable System - Jorge Luiz e Silva; Joelmir José Lopes; Bruno de Abreu Silva; Antonio Carlos Fernandes da Silva (CoRR, 2011)

Power/performance optimization in FPGA-based asymmetric multi-core systems. - Bruno de Abreu Silva; Vanderlei Bonato (FPL, 2012)

Reducing the overall cache miss rate using different cache sizes for Heterogeneous Multi-core Processors. - Bruno de Abreu Silva; Lucas Albers Cuminato; Vanderlei Bonato (ReConFig, 2012)

Parameterizable Ethernet Network-on-Chip Architecture on FPGA. - Helio Fernandes da Cunha Junior; Bruno de Abreu Silva; Vanderlei Bonato (DSD, 2015)

Application-oriented cache memory configuration for energy efficiency in multi-cores. - Bruno de Abreu Silva; Lucas Albers Cuminato; Alexandre C. B. Delbem; Pedro C. Diniz; Vanderlei Bonato (IET Comput. Digit. Tech., 2015)

A method to optimize performance/energy consumption relation for heterogeneous multi-core architectures on FPGA. - Bruno de Abreu Silva (2016)