Chisel Usecase: Designing General Matrix Multiply for FPGA. - Bruno Ferres; Olivier Muller; Frédéric Rousseau 001 (ARC, 2020)

Integrating Quick Resource Estimators in Hardware Construction Framework for Design Space Exploration. - Bruno Ferres; Olivier Muller; Frédéric Rousseau 001 (RSP, 2021)

Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo Theory. - Bruno Ferres; Oussama Oulkaid; Ludovic Henrio; Mehdi Khosravian Ghadikolaei; Matthieu Moy; Gabriel Radanne; Pascal Raymond (DATE, 2023)

A Chisel Framework for Flexible Design Space Exploration through a Functional Approach. - Bruno Ferres; Olivier Muller; Frédéric Rousseau 001 (ACM Trans. Design Autom. Electr. Syst., 2023)

A Transistor Level Relational Semantics for Electrical Rule Checking by SMT Solving. - Oussama Oulkaid; Bruno Ferres; Matthieu Moy; Pascal Raymond; Mehdi Khosravian; Ludovic Henrio; Gabriel Radanne (DATE, 2024)