A First Look at RISC-V Virtualization From an Embedded Systems Perspective. - Bruno Sá; José Martins; Sandro Pinto 001 (IEEE Trans. Computers, 2022)

Holistic RISC-V Virtualization: CVA6-based SoC. - Bruno Sá; Francisco Marques; Manuel Rodriguez; José Martins; Sandro Pinto 001 (CF, 2023)

Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs. - Luca Valente; Asif Veeran; Mattia Sinigaglia; Yvan Tortorella; Alessandro Nadalini; Nils Wistoff; Bruno Sá; Angelo Garofalo; Rafail Psiakis; M. Tolba; Ari Kulmala; Nimisha Limaye; et al. (HCS, 2023)

CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration. - Bruno Sá; Luca Valente; José Martins; Davide Rossi; Luca Benini; Sandro Pinto 001 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

"Interrupting" the Status Quo: A First Glance at the RISC-V Advanced Interrupt Architecture (AIA). - Francisco Marques; Manuel Rodriguez; Bruno Sá; Sandro Pinto 001 (IEEE Access, 2024)

A Heterogeneous RISC-V Based SoC for Secure Nano-UAV Navigation. - Luca Valente; Alessandro Nadalini; Asif Hussain Chiralil Veeran; Mattia Sinigaglia; Bruno Sá; Nils Wistoff; Yvan Tortorella; Simone Benatti; Rafail Psiakis; Ari Kulmala; Baker Mohammad; Sandro Pinto 001; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Evolutionary Algorithms for Metabolic Transformation through Multi-gene Knockout Optimization. - Bruno Sá; Alexandre Oliveira; Miguel Rocha 001 (GECCO, 2025)