Design of low-voltage CMOS pipelined ADCs using 1 pico-Joule of energy per conversion. - Bruno Vaz; Nuno F. Paulino; João Goes; R. Costa; Rui Manuel Tavares; Adolfo Steiger-Garção (ISCAS (1), 2002)

Design and optimization of low-voltage two-stage CMOS amplifiers with enhanced performance. - Rui Manuel Tavares; Bruno Vaz; João Goes; Nuno F. Paulino; Adolfo Steiger-Garção (ISCAS (1), 2003)

Switched-capacitor circuits using a single-phase scheme. - João Goes; Bruno Vaz; Nuno Paulino 002; H. Pinto; Rui Monteiro; Adolfo Steiger-Garção (ISCAS (4), 2005)

A low-voltage 3 mW 10-bit 4MS/s pipeline ADC in digital CMOS for sensor interfacing. - Bruno Vaz; João Goes; R. Piloto; J. Neto; Rui Monteiro; Nuno Paulino 002 (ISCAS (4), 2005)

Low-power low-voltage CMOS A/D sigma-delta modulator for bio-potential signals driven by a single-phase scheme. - João Goes; Nuno Paulino 002; H. Pinto; Rui Monteiro; Bruno Vaz; Adolfo Steiger-Garção (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

A 0.9V ΔΣ Modulator with 80dB SNDR and 83dB DR Using a Single-Phase Technique. - João Goes; Bruno Vaz; Rui Monteiro; Nuno Paulino 002 (ISSCC, 2006)

A programmable RFSoC in 16nm FinFET technology for wideband communications. - Brendan Farley; Christophe Erdmann; Bruno Vaz; John McGrath; Edward Cullen; Bob Verbruggen; Roberto Pelliconi; Daire Breathnach; Peng Lim; Ali Boumaalif; Patrick Lynch; Conrado Mesadri; et al. (A-SSCC, 2017)

16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC. - Bruno Vaz; Adrian Lynam; Bob Verbruggen; Asma Laraba; Conrado Mesadri; Ali Boumaalif; John McGrath; Umanath Kamath; Ronnie De La Torre; Alvin Manlapat; Daire Breathnach; Christophe Erdmann; et al. (ISSCC, 2017)

A modular 16NM Direct-RF TX/RX Embedding 9GS/S DAC and 4.5GS/S ADC with 90DB Isolation and Sub-80PS Channel Alignment for Monolithic Integration in 5G Base-Station SoC. - Christophe Erdmann; Bob Verbruggen; Bruno Vaz; Roberto Pelliconi; John McGrath; Ryan Kinnerk; Ronnie De La Torre; John O'Dwyer; Patrick Lynch; Padraig Kelly; Peng Lim; Daire Breathnach; et al. (VLSI Circuits, 2018)

A 13Bit 5GS/S ADC with Time-Interleaved Chopping Calibration in 16NM FinFET. - Bruno Vaz; Bob Verbruggen; Christophe Erdmann; Diarmuid Collins; John McGrath; Ali Boumaalif; Edward Cullen; Darragh Walsh; Alonso Morgado; Conrado Mesadri; Brian Long; Rajitha Pathepuram; et al. (VLSI Circuits, 2018)

On Creation of Synthetic Samples from GANs for Fake News Identification Algorithms. - Bruno Vaz; Vítor Bernardes; Álvaro Figueira (WorldCIST (3), 2022)

GANs in the Panorama of Synthetic Data Generation Methods. - Bruno Vaz; Álvaro Figueira (ACM Trans. Multim. Comput. Commun. Appl., 2025)