A portable digital DLL for high-speed CMOS interface circuits. - Bruno W. Garlepp; Kevin S. Donnelly; Jun Kim; Pak Shing Chau; Jared L. Zerbe; Charlie Huang; Chanh Tran; Clemenz L. Portmann; Donald Stark 001; Yiu-Fai Chan; Thomas H. Lee; Mark A. Horowitz (IEEE J. Solid State Circuits, 1999)

1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus. - Jared L. Zerbe; Pak Shing Chau; Carl W. Werner; Timothy P. Thrush; H. J. Liaw; Bruno W. Garlepp; Kevin S. Donnelly (IEEE J. Solid State Circuits, 2001)

Modeling, simulation, and design of a multi-mode 2-10 Gb/sec fully adaptive serial link system. - Carl W. Werner; C. Hoyer; Andrew Ho; Metha Jeeradit; Fred Chen; Bruno W. Garlepp; Bill Stonecypher; Simon Li; Akash Bansal; Amita Agarwal; Elad Alon; Vladimir Stojanovic; et al. (CICC, 2005)

Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery. - Vladimir Stojanovic; Andrew Ho; Bruno W. Garlepp; Fred Chen; Jason Wei; Grace Tsang; Elad Alon; Ravi T. Kollipara; Carl W. Werner; Jared L. Zerbe; Mark A. Horowitz (IEEE J. Solid State Circuits, 2005)

A 2.5Gb/s Multi-Rate 0.25µm CMOS CDR Utilizing a Hybrid Analog/Digital Loop Filter. - Michael H. Perrott; Yunteng Huang; Rex T. Baird; Bruno W. Garlepp; Ligang Zhang; Jerrell P. Hein (ISSCC, 2006)

A monolithic low-bandwidth jitter-cleaning PLL with hitless switching for SONET/SDH clock generation. - Derrick C. Wei; Yunteng Huang; Bruno W. Garlepp; Jerrell P. Hein (ISSCC, 2006)

A 2.5-Gb/s Multi-Rate 0.25-$ mu$m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition. - Michael H. Perrott; Yunteng Huang; Rex T. Baird; Bruno W. Garlepp; Douglas Pastorello; Eric T. King; Qicheng Yu; Dan B. Kasha; Philip Steiner; Ligang Zhang; Jerrell P. Hein; Bruce Del Signore (IEEE J. Solid State Circuits, 2006)

A new technique for characterization of digital-to-analog converters in high-speed systems. - Jafar Savoj; Ali-Azam Abbasfar; Amir Amirkhany; Bruno W. Garlepp; Mark A. Horowitz (DATE, 2007)

A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR. - Brian S. Leibowitz; Jade Kizer; Haechang Lee; Fred Chen; Andrew Ho; Metha Jeeradit; Akash Bansal; Trey Greer; Simon Li; Ramin Farjad-Rad; William F. Stonecypher; Yohan Frans; et al. (ISSCC, 2007)

A 24 Gb/s Software Programmable Analog Multi-Tone Transmitter. - Amir Amirkhany; Aliazam Abbasfar; Jafar Savoj; Metha Jeeradit; Bruno W. Garlepp; Ravi T. Kollipara; Vladimir Stojanovic; Mark Horowitz (IEEE J. Solid State Circuits, 2008)

A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter for Backplane Communications. - Jafar Savoj; Aliazam Abbasfar; Amir Amirkhany; Metha Jeeradit; Bruno W. Garlepp (IEEE J. Solid State Circuits, 2008)

A low-area switched-resistor loop-filter technique for fractional-N synthesizers applied to a MEMS-based programmable oscillator. - Michael H. Perrott; Sudhakar Pamarti; Eric G. Hoffman; Fred S. Lee; Shouvik Mukherjee; Cathy Lee; Vadim Tsinker; Sathi Perumal; Benjamin Soto; Niveditha Arumugam; Bruno W. Garlepp (ISSCC, 2010)

A Low Area, Switched-Resistor Based Fractional-N Synthesizer Applied to a MEMS-Based Programmable Oscillator. - Michael H. Perrott; Sudhakar Pamarti; Eric G. Hoffman; Fred S. Lee; Shouvik Mukherjee; Cathy Lee; Vadim Tsinker; Sathi Perumal; Benjamin Soto; Niveditha Arumugam; Bruno W. Garlepp (IEEE J. Solid State Circuits, 2010)