An 8-Gb/s simultaneous bidirectional link with on-die waveform capture. - Bryan Casper; Aaron Martin; James E. Jaussi; Joe Kennedy 001; Randy Mooney (IEEE J. Solid State Circuits, 2003)

Analysis of PLL clock jitter in high-speed serial links. - Pavan Kumar Hanumolu; Bryan Casper; Randy Mooney; Gu-Yeon Wei; Un-Ku Moon (IEEE Trans. Circuits Syst. II Express Briefs, 2003)

Jitter in high-speed serial and parallel links. - Pavan Kumar Hanumolu; Bryan Casper; Randy Mooney; Gu-Yeon Wei; Un-Ku Moon (ISCAS (4), 2004)

8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew. - James E. Jaussi; Ganesh Balamurugan; David R. Johnson; Bryan Casper; Aaron Martin; Joseph T. Kennedy; Naresh R. Shanbhag; Randy Mooney (IEEE J. Solid State Circuits, 2005)

A 20Gb/s Forwarded Clock Transceiver in 90nm CMOS B. - Bryan Casper; James E. Jaussi; Frank O'Mahony; Mozhgan Mansuri; K. Canagasaby; Joseph T. Kennedy; E. Yeung; Randy Mooney (ISSCC, 2006)

A 20Gb/s Embedded Clock Transceiver in 90nm CMOS. - Bryan Casper; James E. Jaussi; Frank O'Mahony; Mozhgan Mansuri; K. Canagasaby; Joe Kennedy 001; Randy Mooney (ISSCC, 2006)

Testing High-Speed IO Links Using On-Die Circuitry. - Priya Iyer; Shailendra Jain; Bryan Casper; Jason Howard (VLSI Design, 2006)

Future Microprocessor Interfaces: Analysis, Design and Optimization. - Bryan Casper; Ganesh Balamurugan; James E. Jaussi; Joseph T. Kennedy; Mozhgan Mansuri (CICC, 2007)

Strong injection locking of low-Q LC oscillators. - Mozhgan Mansuri; Frank O'Mahony; Ganesh Balamurugan; James E. Jaussi; Joseph T. Kennedy; Sudip Shekhar; Randy Mooney; Bryan Casper (CICC, 2008)

A 27Gb/s Forwarded-Clock I/O Receiver Using an Injection-Locked LC-DCO in 45nm CMOS. - Frank O'Mahony; Sudip Shekhar; Mozhgan Mansuri; Ganesh Balamurugan; James E. Jaussi; Joseph T. Kennedy; Bryan Casper; David J. Allstot; Randy Mooney (ISSCC, 2008)

A Scalable 5-15 Gbps, 14-75 mW Low-Power I/O Transceiver in 65 nm CMOS. - Ganesh Balamurugan; Joseph T. Kennedy; Gaurab Banerjee; James E. Jaussi; Mozhgan Mansuri; Frank O'Mahony; Bryan Casper; Randy Mooney (IEEE J. Solid State Circuits, 2008)

Clocking Analysis, Implementation and Measurement Techniques for High-Speed Data Links - A Tutorial. - Bryan Casper; Frank O'Mahony (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Strong Injection Locking in Low- Q LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver. - Sudip Shekhar; Ganesh Balamurugan; David J. Allstot; Mozhgan Mansuri; James E. Jaussi; Randy Mooney; Joseph T. Kennedy; Bryan Casper; Frank O'Mahony (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A 5-to-25Gb/s 1.6-to-3.8mW/(Gb/s) reconfigurable transceiver in 45nm CMOS. - Ganesh Balamurugan; Frank O'Mahony; Mozhgan Mansuri; James E. Jaussi; Joseph T. Kennedy; Bryan Casper (ISSCC, 2010)

A 47×10Gb/s 1.4mW/(Gb/s) parallel interface in 45nm CMOS. - Frank O'Mahony; Joseph T. Kennedy; James E. Jaussi; Ganesh Balamurugan; Mozhgan Mansuri; Clark Roberts; Sudip Shekhar; Randy Mooney; Bryan Casper (ISSCC, 2010)

A 47 , ˟, 10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS. - Frank O'Mahony; James E. Jaussi; Joseph T. Kennedy; Ganesh Balamurugan; Mozhgan Mansuri; Clark Roberts; Sudip Shekhar; Randy Mooney; Bryan Casper (IEEE J. Solid State Circuits, 2010)

An on-die all-digital delay measurement circuit with 250fs accuracy. - Mozhgan Mansuri; Bryan Casper; Frank O'Mahony (VLSIC, 2012)

Design considerations for low-power receiver front-end in high-speed data links. - Sudip Shekhar; James E. Jaussi; Frank O'Mahony; Mozhgan Mansuri; Bryan Casper (CICC, 2013)

A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS. - Mozhgan Mansuri; James E. Jaussi; Joseph T. Kennedy; Tzu-Chien Hsueh; Sudip Shekhar; Ganesh Balamurugan; Frank O'Mahony; Clark Roberts; Randy Mooney; Bryan Casper (ISSCC, 2013)

A Scalable 0.128-1 Tb/s, 0.8-2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS. - Mozhgan Mansuri; James E. Jaussi; Joseph T. Kennedy; Tzu-Chien Hsueh; Sudip Shekhar; Ganesh Balamurugan; Frank O'Mahony; Clark Roberts; Randy Mooney; Bryan Casper (IEEE J. Solid State Circuits, 2013)

26.4 A 25.6Gb/s differential and DDR4/GDDR5 dual-mode transmitter with digital clock calibration in 22nm CMOS. - Tzu-Chien Hsueh; Ganesh Balamurugan; James E. Jaussi; Sami Hyvonen; Joseph T. Kennedy; Gökçe Keskin; Tawfiq Musah; Sudip Shekhar; Rajesh Inti; Shreyas Sen; Mozhgan Mansuri; Clark Roberts; et al. (ISSCC, 2014)

26.2 A 205mW 32Gb/s 3-Tap FFE/6-tap DFE bidirectional serial link in 22nm CMOS. - James E. Jaussi; Ganesh Balamurugan; Sami Hyvonen; Tzu-Chien Hsueh; Tawfiq Musah; Gökçe Keskin; Sudip Shekhar; Joseph T. Kennedy; Shreyas Sen; Rajesh Inti; Mozhgan Mansuri; Michael Leddige; et al. (ISSCC, 2014)

A 4-32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS. - Tawfiq Musah; James E. Jaussi; Ganesh Balamurugan; Sami Hyvonen; Tzu-Chien Hsueh; Gokce Keskin; Sudip Shekhar; Joseph T. Kennedy; Shreyas Sen; Rajesh Inti; Mozhgan Mansuri; Michael Leddige; et al. (IEEE J. Solid State Circuits, 2014)

A 0.5-to-0.75V, 3-to-8 Gbps/lane, 385-to-790 fJ/b, bi-directional, quad-lane forwarded-clock transceiver in 22nm CMOS. - Rajesh Inti; Sudip Shekhar; Ganesh Balamurugan; James E. Jaussi; Clark Roberts; Tzu-Chien Hsueh; Bryan Casper (VLSIC, 2015)

A 1.2-5Gb/s 1.4-2pJ/b serial link in 22nm CMOS with a direct data-sequencing blind oversampling CDR. - Sudip Shekhar; Rajesh Inti; James E. Jaussi; Tzu-Chien Hsueh; Bryan Casper (VLSIC, 2015)

An On-Die All-Digital Power Supply Noise Analyzer With Enhanced Spectrum Measurements. - Tzu-Chien Hsueh; Frank O'Mahony; Mozhgan Mansuri; Bryan Casper (IEEE J. Solid State Circuits, 2015)

23.2 A 32Gb/s bidirectional 4-channel 4pJ/b capacitively coupled link in 14nm CMOS for proximity communication. - Chintan Thakkar; Shreyas Sen; James E. Jaussi; Bryan Casper (ISSCC, 2016)

A 32 Gb/s Bidirectional 4-channel 4 pJ/b Capacitively Coupled Link in 14 nm CMOS for Proximity Communication. - Chintan Thakkar; Shreyas Sen; James E. Jaussi; Bryan Casper (IEEE J. Solid State Circuits, 2016)

A 25 Gb/s 60 GHz digital power amplifier in 28nm CMOS. - Kaushik Dasgupta; Saeid Daneshgar; Chintan Thakkar; Kunal Datta; James E. Jaussi; Bryan Casper (ESSCIRC, 2017)

High-speed contactless I/O for computing devices. - Chintan Thakkar; James E. Jaussi; Bryan Casper (CICC, 2018)

A 112 Gb/s PAM4 Linear TIA with 0.96 pJ/bit Energy Efficiency in 28 nm CMOS. - Hao Li 047; Ganesh Balamurugan; James E. Jaussi; Bryan Casper (ESSCIRC, 2018)

A 27.8Gb/s 11.5pJ/b 60GHz transceiver in 28nm CMOS with polarization MIMO. - Saeid Daneshgar; Kaushik Dasgupta; Chintan Thakkar; Anandaroop Chakrabarti; Shuhei Yamada; Debabani Choudhury; James E. Jaussi; Bryan Casper (ISSCC, 2018)

A 40Gb/s 6pJ/b RX baseband in 28nm CMOS for 60GHz polarization MIMO. - Shinwon Kang; Chintan Thakkar; Nathan Narevsky; Kaushik Dasgupta; Saeid Daneshgar; James E. Jaussi; Bryan Casper (ISSCC, 2018)

A Digital-Intensive 2-to-9.2 GB/S/Pin Memory Controller I/O with Fast-Response LDO in 10NM CMOS. - Rajesh Inti; Mozhgan Mansuri; Joe Kennedy 001; Hariprasath Venkatram; Chun-Ming Hsu; Aaron Martin; James E. Jaussi; Bryan Casper (VLSI Circuits, 2018)

A 60-GHz Transceiver and Baseband With Polarization MIMO in 28-nm CMOS. - Kaushik Dasgupta; Saeid Daneshgar; Chintan Thakkar; Shinwon Kang; Anandaroop Chakrabarti; Shuhei Yamada; Nathan Narevsky; Debabani Choudhury; James E. Jaussi; Bryan Casper (IEEE J. Solid State Circuits, 2018)

A 42.2Gb/s 4.3pJ/b 60GHz Digital Transmitter with 12b/Symbol Polarization MIMO. - Chintan Thakkar; Stefan Shopov; Anandaroop Chakrabarti; Shuhei Yamada; Debabani Choudhury; James E. Jaussi; Bryan Casper (ISSCC, 2019)

A 112 Gb/s PAM4 Transmitter with Silicon Photonics Microring Modulator and CMOS Driver. - Hao Li 047; Ganesh Balamurugan; Meer Sakib 001; Jie Sun; Jeffery Driscoll; Ranjeet Kumar; Hasitha Jayatilleka; Haisheng Rong; James E. Jaussi; Bryan Casper (OFC, 2019)

A Low-Power Bidirectional Link With a Direct Data-Sequencing Blind Oversampling CDR. - Sudip Shekhar; Rajesh Inti; James E. Jaussi; Tzu-Chien Hsueh; Bryan Casper (IEEE J. Solid State Circuits, 2019)

A 42.2-Gb/s 4.3-pJ/b 60-GHz Digital Transmitter With 12-b/Symbol Polarization MIMO. - Chintan Thakkar; Anandaroop Chakrabarti; Shuhei Yamada; Debabani Choudhury; James E. Jaussi; Bryan Casper (IEEE J. Solid State Circuits, 2019)

4.5 A 64Gb/s 1.4pJ/b/element 60GHz 2×2-Element Phased-Array Receiver with 8b/symbol Polarization MIMO and Spatial Interference Tolerance. - Anandaroop Chakrabarti; Chintan Thakkar; Shuhei Yamada; Debabani Choudhury; James E. Jaussi; Bryan Casper (ISSCC, 2020)

12.1 A 3D-Integrated Microring-Based 112Gb/s PAM-4 Silicon-Photonic Transmitter with Integrated Nonlinear Equalization and Thermal Control. - Hao Li 047; Ganesh Balamurugan; Meer Sakib 001; Ranjeet Kumar; Hasitha Jayatilleka; Haisheng Rong; James E. Jaussi; Bryan Casper (ISSCC, 2020)

A Scalable 32-to-56Gb/s 0.56-to-1.28pJ/b Voltage-Mode VCSEL-Based Optical Transmitter in 28nm CMOS. - Rajesh Inti; Mozhgan Mansuri; Joe Kennedy 001; Junyi Qiu; Chun-Ming Hsu; Jahnavi Sharma; Hao Li 047; Bryan Casper; James E. Jaussi (CICC, 2021)

A 3-D-Integrated Silicon Photonic Microring-Based 112-Gb/s PAM-4 Transmitter With Nonlinear Equalization and Thermal Control. - Hao Li 047; Ganesh Balamurugan; Taehwan Kim; Meer Sakib 001; Ranjeet Kumar; Haisheng Rong; James E. Jaussi; Bryan Casper (IEEE J. Solid State Circuits, 2021)

A Scalable 32-56 Gb/s 0.56-1.28 pJ/b Voltage-Mode VCSEL-Based Optical Transmitter in 28-nm CMOS. - Mozhgan Mansuri; Rajesh Inti; Joe Kennedy 001; Junyi Qiu; Chun-Ming Hsu; Jahnavi Sharma; Hao Li 047; Bryan Casper; James E. Jaussi (IEEE J. Solid State Circuits, 2022)