Computer aided design techniques applied to logic design. - Bulent I. Dervisoglu (1973)

Hardware description languages in Great Britain. - Bulent I. Dervisoglu (Computer, 1974)

Theory and Design of Mixed-Mode Sequential Machines. - Bulent I. Dervisoglu; Howard A. Sholl (IEEE Trans. Computers, 1980)

A Hard Progammable Control Unit Design Using VLSI Technology. - Bulent I. Dervisoglu; Donald J. Criscione (IEEE Trans. Computers, 1981)

On Coosing a Hardware Descriptive Language for Digital Systems Testing/Verification. - Bulent I. Dervisoglu (ITC, 1984)

Using Scan Technology for Debug and Diagnostics in a Workstation Environment. - Bulent I. Dervisoglu (ITC, 1988)

ATLAS/ELA: Scan-based Software Tools for Reducing System Debug Time in a State-of-the-art Workstation. - Bulent I. Dervisoglu; M. A. Keil (DAC, 1989)

Scan-path architecture for pseudorandom testing. - Bulent I. Dervisoglu (IEEE Des. Test, 1989)

Towards a standard approach for controlling board-level test functions. - Bulent I. Dervisoglu (ITC, 1990)

Application of scan hardware and software for debug and diagnostics in a workstation environment. - Bulent I. Dervisoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement. - Bulent I. Dervisoglu; Gayvin E. Stong (ITC, 1991)

Application of Scan-Based DFT Methodology for Detecting Static and Timing Failures in VLSI Components. - Bulent I. Dervisoglu; Gayvin E. Stong (VLSI, 1991)

Features of a Scan and Clock Resource chip for providing access to board-level test functions. - Bulent I. Dervisoglu (J. Electron. Test., 1991)

Boundary-Scan Update: IEEE P1149.2 Description and Status Report. - Bulent I. Dervisoglu (IEEE Des. Test Comput., 1992)

Microprocessor Testing: Which Technique is Best? (Panel). - Jacob A. Abraham; Sandip Kundu; Janak H. Patel; Manuel A. d'Abreu; Bulent I. Dervisoglu; Marc E. Levitt; Hector R. Sucar; Ron G. Walther (DAC, 1994)

Special Report: Shared-I/O Scan Test. - Bulent I. Dervisoglu (IEEE Des. Test Comput., 1995)

Shared I/O-cell structures: a framework for extending the IEEE 1149.1 boundary-scan standard. - Bulent I. Dervisoglu; Mike Ricchetti; William Eklow (ITC, 1998)

Design for testability: it is time to deliver it for Time-to-Market. - Bulent I. Dervisoglu (ITC, 1999)

A Unified DFT Architecture for Use with IEEE 1149.1 and VSIA/IEEE P1500 Compliant Test Access Controllers. - Bulent I. Dervisoglu (DAC, 2001)

Reducing Time to Volume and Time to Market: Is Silicon Debug and Diagnosis the Answer? - Fidel Muradali; Mike Ricchetti; Bart Vermeulen; Bulent I. Dervisoglu; Bob Gottlieb; Bernd Koenemann; C. J. Clark (VTS, 2002)