Design and Implementation of Viterbi Decoder Using FPGAs. - Bupesh Pandita; Subir K. Roy (VLSI Design, 1999)

Designing Complex Delta Sigma Modulators with Signal-Transfer Functions having Good Stop-Band Attenuation. - Bupesh Pandita; Kenneth W. Martin (ISCAS, 2007)

Oversampling A/D Converters With Reduced Sensitivity to DAC Nonlinearities. - Bupesh Pandita; Kenneth W. Martin (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Delay calibration circuit for delay lines. - Bupesh Pandita (ISCAS, 2015)

A Low-Ripple Resistor-Less Hybrid Loop Filter based PLL in 3nm FinFET. - Ping Lu; Charlie Boecker; Bupesh Pandita; Minhan Chen; Sheethal Nayak (ISCAS, 2022)

Reference Clock Jitter Immunity by Accurate DPLL Bandwidth Control in a Multiple-link Die-to-Die Interface. - Ping Lu; Bupesh Pandita; Minhan Chen (MWSCAS, 2023)