An adaptive bilateral motion estimation algorithm and its hardware architecture. - Abdulkadir Akin; Mert Cetin; Burak Erbagci; Ozgur Karakaya; Ilker Hamzaoglu (VLSI-SoC, 2010)

An adaptive bilateral motion estimation algorithm and its hardware architecture. - Abdulkadir Akin; Mert Cetin; Tevfik Zafer Ozcan; Burak Erbagci; Ilker Hamzaoglu (IEEE Trans. Consumer Electron., 2012)

A 32kB secure cache memory with dynamic replacement mapping in 65nm bulk CMOS. - Burak Erbagci; Fangfei Liu; Cagla Cakir; Nail Etkin Can Akkaya; Ruby B. Lee; Ken Mai (A-SSCC, 2015)

A 275 Gbps AES encryption accelerator using ROM-based S-boxes in 65nm. - Burak Erbagci; Nail Etkin Can Akkaya; Craig Teegarden; Ken Mai (CICC, 2015)

A DPA-resistant self-timed three-phase dual-rail pre-charge logic family. - Nail Etkin Can Akkaya; Burak Erbagci; Raymond Carley; Ken Mai (HOST, 2015)

Deeply hardware-entangled reconfigurable logic and interconnect. - Burak Erbagci; Mudit Bhargava; Rachel Dondero; Ken Mai (ReConFig, 2015)

A secure camouflaged threshold voltage defined logic family. - Burak Erbagci; Cagri Erbagci; Nail Etkin Can Akkaya; Ken Mai (HOST, 2016)

Secure chip odometers using intentional controlled aging. - Nail Etkin Can Akkaya; Burak Erbagci; Ken Mai (HOST, 2018)

A compact energy-efficient pseudo-static camouflaged logic family. - Prashanth Mohan; Nail Etkin Can Akkaya; Burak Erbagci; Ken Mai (HOST, 2018)

A secure camouflaged logic family using post-manufacturing programming with a 3.6GHz adder prototype in 65nm CMOS at 1V nominal VDD. - Nail Etkin Can Akkaya; Burak Erbagci; Ken Mai (ISSCC, 2018)

An Inherently Secure FPGA using PUF Hardware-Entanglement and Side-Channel Resistant Logic in 65nm Bulk CMOS. - Burak Erbagci; Nail Etkin Can Akkaya; Cagri Erbagci; Ken Mai (ESSCIRC, 2019)

Secure hardware-entangled field programmable gate arrays. - Burak Erbagci; Nail Etkin Can Akkaya; Mudit Bhargava; Rachel Dondero; Ken Mai (J. Parallel Distributed Comput., 2019)

15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications. - Qing Dong 001; Mahmut E. Sinangil; Burak Erbagci; Dar Sun; Win-San Khwa; Hung-Jen Liao; Yih Wang; Jonathan Chang (ISSCC, 2020)

A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS. - Mahmut E. Sinangil; Burak Erbagci; Rawan Naous; Kerem Akarvardar; Dar Sun; Win-San Khwa; Hung-Jen Liao; Yih Wang; Jonathan Chang (IEEE J. Solid State Circuits, 2021)