A Hardware Intensive Approach for Efficient Implementation of Numerical Integration for FPGA Platforms. - Burhan Khurshid; Roohie Naaz Mir (VLSID, 2014)

High Efficiency Generalized Parallel Counters for Xilinx FPGAs. - Burhan Khurshid; Roohie Naaz Mir (HiPC, 2015)

High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs. - Burhan Khurshid; Roohie Naaz Mir (Int. J. Reconfigurable Comput., 2015)

Technology optimised fixed-point bit-parallel multiplier for LUT-based FPGAs. - Burhan Khurshid; Roohie Naaz Mir (Int. J. High Perform. Syst. Archit., 2016)

An Efficient FIR Filter Structure Based on Technology-Optimized Multiply-Adder Unit Targeting LUT-Based FPGAs. - Burhan Khurshid; Roohie Naaz Mir (Circuits Syst. Signal Process., 2017)

LUT based realization of fixed-point multipliers targeting state-of-art FPGAs. - Burhan Khurshid (Des. Autom. Embed. Syst., 2017)

Efficient Realization of Fixed-Point Binary and Ternary Adders on FPGAs. - Burhan Khurshid; Roohie Naaz Mir (J. Circuits Syst. Comput., 2017)

Technology-Optimized Fixed-Point Bit-Parallel Multipliers for FPGAs. - Burhan Khurshid (J. Signal Process. Syst., 2017)

Improved Synthesis of Generalized Parallel Counters on FPGAs Using Only LUTs. - Burhan Khurshid (J. Circuits Syst. Comput., 2018)

An Efficient Fixed-Point Multiplier Based on CORDIC Algorithm. - Burhan Khurshid; Javeed Jeelani Khan (J. Circuits Syst. Comput., 2021)

High-performance CORDIC-based approximate MAC architectures for FPGA platforms. - Burhan Khurshid (Integr., 2025)