Throughput enhancement for a new time-delay sampled-data system based True Random Bit Generator. - Ramazan Yeniceri; Buse Ustaoglu; Müstak E. Yalçin (ECCTD, 2013)

Fault tolerant register file design for MIPS AES-crypto microprocessor. - Buse Ustaoglu; Berna Örs Yalçin (ICECS, 2015)

Creating test environment with UVM for SPI. - Buse Ustaoglu; Ahmet Cagri Bagbaba; Berna Örs; Inan Erdem (SIU, 2015)

Reliability analysis of MIPS-32 microprocessor register files designed with different fault tolerant techniques. - Buse Ustaoglu; Berna Örs Yalçin (SIU, 2016)

SAT-Lancer: A Hardware SAT-Solver for Self-Verification. - Buse Ustaoglu; Sebastian Huhn 001; Daniel Große; Rolf Drechsler (ACM Great Lakes Symposium on VLSI, 2018)

(ReCo)Fuse Your PRC or Lose Security: Finally Reliable Reconfiguration-Based Countermeasures on FPGAs. - Kenneth Schmitz; Buse Ustaoglu; Daniel Große; Rolf Drechsler (ARC, 2019)

SAT-Hard: A Learning-Based Hardware SAT-Solver. - Buse Ustaoglu; Sebastian Huhn 001; Frank Sill Torres; Daniel Große; Rolf Drechsler (DSD, 2019)

Hardware packages for self-verification and secure partial reconfiguration / von Buse Ustaoğlu. - Buse Ustaoglu (2022)