A 576 Mb DRAM with 16-channel 10.3125Gbps serial I/O and 14.5 ns latency. - Socrates D. Vamvakos; Bendik Kleveland; Dipak K. Sikdar; B. K. Ahuja; Haidang Lin; Jayaprakash Balachandran; Wignes Balakrishnan; Aldo Bottelli; Jawji Chen; Xiaole Chen; Jae Choi; Jeong Choi; et al. (ESSCIRC, 2012)

Early detection and repair of VRT and aging DRAM bits by margined in-field BIST. - Bendik Kleveland; Jeong Choi; Jeff Kumala; Pascal Adam; Patrick Chen; Rajesh Chopra; Antonio Cruz; Ronald B. David; Ashish Dixit; Sinan Doluca; Mark Hendrickson; Ben Lee; et al. (VLSIC, 2014)