A fixed-point 3D graphics library with energy-efficient cache architecture for mobile multimedia systems. - Min-wuk Lee; Byeong-Gyu Nam; Ju-Ho Sohn; Namjun Cho; Hyejung Kim; Kwanho Kim; Hoi-Jun Yoo (ISCAS (5), 2005)

Development of a 3-D graphics rendering engine with lighting acceleration for handheld multimedia systems. - Byeong-Gyu Nam; Min-wuk Lee; Hoi-Jun Yoo (IEEE Trans. Consumer Electron., 2005)

A 231-MHz, 2.18-mW 32-bit Logarithmic Arithmetic Unit for Fixed-Point 3-D Graphics System. - Hyejung Kim; Byeong-Gyu Nam; Ju-Ho Sohn; Jeong-Ho Woo; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2006)

A low-power handheld GPU using logarithmic arithmetic and triple DVFS power domains. - Byeong-Gyu Nam; Jeabin Lee; Kwanho Kim; Seungjin Lee 001; Hoi-Jun Yoo (Graphics Hardware, 2007)

A low-power vector processor using logarithmic arithmetic for handheld 3d graphics systems. - Byeong-Gyu Nam; Hoi-Jun Yoo (ESSCIRC, 2007)

A Power Management Unit with Continuous Co-Locking of Clock Frequency and Supply Voltage for Dynamic Voltage and Frequency Scaling. - Jeabin Lee; Byeong-Gyu Nam; Seong-Jun Song; Namjun Cho; Hoi-Jun Yoo (ISCAS, 2007)

A 52.4mW 3D Graphics Processor with 141Mvertices/s Vertex Shader and 3 Power Domains of Dynamic Voltage and Frequency Scaling. - Byeong-Gyu Nam; Jeabin Lee; Kwanho Kim; Seungjin Lee 001; Hoi-Jun Yoo (ISSCC, 2007)

A Low-Power Unified Arithmetic Unit for Programmable Handheld 3-D Graphics Systems. - Byeong-Gyu Nam; Hyejung Kim; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2007)

Cost-effective low-power graphics processing unit for handheld devices. - Byeong-Gyu Nam; Jeabin Lee; Kwanho Kim; Seungjin Lee 001; Hoi-Jun Yoo (IEEE Commun. Mag., 2008)

Power and Area-Efficient Unified Computation of Vector and Elementary Functions for Handheld 3D Graphics Systems. - Byeong-Gyu Nam; Hyejung Kim; Hoi-Jun Yoo (IEEE Trans. Computers, 2008)

An Embedded Stream Processor Core Based on Logarithmic Arithmetic for a Low-Power 3-D Graphics SoC. - Byeong-Gyu Nam; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2009)

Design of "green" high-performance processor circuits. - Tobias Noll; Raney Southerland; Vladimir Stojanovic; Sonia Leon; Lew Chua-Eoan; Alice Wang; Byeong-Gyu Nam; Masaya Sumita (ISSCC, 2011)

Session 12 overview: Multimedia and communications SoCs: Energy-efficient digital subcommittee. - Byeong-Gyu Nam; Shannon Morton (ISSCC, 2012)

A high-throughput 16× super resolution processor for real-time object recognition SoC. - Junyoung Park 002; Byeong-Gyu Nam; Hoi-Jun Yoo (ESSCIRC, 2013)

A 57 mW 12.5 µJ/Epoch Embedded Mixed-Mode Neuro-Fuzzy Processor for Mobile Real-Time Object Recognition. - Jinwook Oh; Gyeonghoon Kim; Byeong-Gyu Nam; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2013)

A 27mW reconfigurable marker-less logarithmic camera pose estimation engine for mobile augmented reality processor. - Injoon Hong; Gyeonghoon Kim; Youchang Kim; Donghyun Kim; Byeong-Gyu Nam; Hoi-Jun Yoo (A-SSCC, 2014)

Highlights of the ISSCC 2013 Processors and High Performance Digital Sessions. - Timothy C. Fischer; Byeong-Gyu Nam; Leland Chang; Tadahiro Kuroda; Michiel A. P. Pertijs (IEEE J. Solid State Circuits, 2014)

Intelligent Network-on-Chip With Online Reinforcement Learning for Portable HD Object Recognition Processor. - Junyoung Park 002; Injoon Hong; Gyeonghoon Kim; Byeong-Gyu Nam; Hoi-Jun Yoo (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

A 27 mW Reconfigurable Marker-Less Logarithmic Camera Pose Estimation Engine for Mobile Augmented Reality Processor. - Injoon Hong; Gyeonghoon Kim; Youchang Kim; Donghyun Kim; Byeong-Gyu Nam; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2015)

A low-power real-time hidden Markov model accelerator for gesture user interface on wearable devices. - Seongrim Choi; Jaemin Hwang; Suhwan Cho; Ara Kim; Byeong-Gyu Nam (A-SSCC, 2016)

A self-powered always-on vision-based wake-up detector for wearable gesture user interfaces. - Suhwan Cho; Seongrim Choi; Junsik Woo; Ara Kim; Byeong-Gyu Nam (A-SSCC, 2017)

Session 3 overview: Digital processors. - Thomas Burd; James Myers; Byeong-Gyu Nam (ISSCC, 2017)

Session 14 overview: Deep-learning processors. - Takashi Hashimoto; Mahesh Mehendale; Byeong-Gyu Nam (ISSCC, 2017)

Session 2 overview: Processors: Digital architectures and systems subcommittee. - Thomas Burd; Muhammad M. Khellah; Byeong-Gyu Nam (ISSCC, 2018)

Session 13 overview: Machine learning and signal processing: Digital architectures and systems subcommittee. - Dejan Markovic; Masato Motomura; Byeong-Gyu Nam (ISSCC, 2018)

Compact Mixed-Signal Convolutional Neural Network Using a Single Modular Neuron. - Dong-Jin Chang; Byeong-Gyu Nam; Seung-Tak Ryu (IEEE Trans. Circuits Syst., 2020)

MixedNet: Network Design Strategies for Cost-Effective Quantized CNNs. - Dong-Jin Chang; Byeong-Gyu Nam; Seung-Tak Ryu (IEEE Access, 2021)

RNPE: An MSDF and Redundant Number System-Based DNN Accelerator Engine. - Iraj Moghaddasi; Ghassem Jaberipur; Danial Javaheri; Byeong-Gyu Nam (IEEE Access, 2024)

Enhancing Computation-Efficiency of Deep Neural Network Processing on Edge Devices through Serial/Parallel Systolic Computing. - Iraj Moghaddasi; Byeong-Gyu Nam (Mach. Learn. Knowl. Extr., 2024)

FSSA: A Fully Serial and Mixed-Precision Systolic Array for Vision Transformer Acceleration on Edge. - Iraj Moghaddasi; Byeong-Gyu Nam (IEEE Access, 2025)