A 264-to-287GHz, -2.5dBm Output Power, and -92dBc/Hz 1MHz-Phase-Noise CMOS Signal Source Adopting a 75fsrms Jitter D-Band Cascaded Sub-Sampling PLL. - Byeong-Taek Moon; Sang-Gug Lee 001; Jaehyouk Choi (ISSCC, 2023)

Analysis and Design of Power-Efficient H-Band CMOS Frequency Doubler Employing Gain Boosting and Harmonic Enhancing Techniques. - Byeong-Taek Moon; Byeonghun Yun; Jusung Kim; Sang-Gug Lee 001 (IEEE Access, 2023)

10.8 A 281GHz, -1.5dBm Output-Power CMOS Signal Source Adopting a 46fsrms Jitter D-Band Cascaded Subharmonically Injection-Locked Sub-Sampling PLL with a 274MHz Reference. - Byeong-Taek Moon; Hyun-Chul Park; Sang-Gug Lee 001 (ISSCC, 2024)