FIR Filter Synthesis Based on Interleaved Processing of Coefficient Generation and Multiplier-Block Synthesis. - Byeong Yong Kong; In-Cheol Park (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Adaptive Metric Calculation for Improving Detection Capability of MIMO Detectors. - Byeong Yong Kong; In-Cheol Park (VTC Spring, 2013)

Efficient Tree-Traversal Strategy for Soft-Output MIMO Detection Based on Candidate-Set Reorganization. - Byeong Yong Kong; In-Cheol Park (IEEE Commun. Lett., 2013)

Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes. - Byeong Yong Kong; Jihyuck Jo; Hyewon Jeong; Mina Hwang; Soyoung Cha; Bongjin Kim; In-Cheol Park (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Narrow-range frequency estimation based on comprehensive optimization of DFT and interpolation. - Byeong Yong Kong; In-Cheol Park (ICASSP, 2015)

Low-complexity symbol detection for massive MIMO uplink based on Jacobi method. - Byeong Yong Kong; In-Cheol Park (PIMRC, 2016)

Efficient Sorting Architecture for Successive-Cancellation-List Decoding of Polar Codes. - Byeong Yong Kong; Hoyoung Yoo; In-Cheol Park (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Improved Sorting Architecture for K-Best MIMO Detection. - Byeong Yong Kong; In-Cheol Park (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Interference Cancellation Architecture for Pipelined Parallel MIMO Detectors. - Byeong Yong Kong; Jaehwan Jung; In-Cheol Park (ICECS, 2018)

Efficient Implementation of Multiple Interleavers in IDMA for 5G. - Byeong Yong Kong; In-Cheol Park (ISOCC, 2018)

A Memory-Efficient IDMA Architecture Based on On-the-Fly Despreading. - Byeong Yong Kong; In-Cheol Park (IEEE J. Solid State Circuits, 2018)

Parallel IDMA Architecture Based on Interleaving with Replicated Subpatterns. - Byeong Yong Kong; In-Cheol Park (ICC, 2019)

Improved Parallel-IDMA Architecture with Low-Complexity Elementary Signal Estimators. - Byeong Yong Kong (ISCAS, 2020)

Ultra-Low-Latency LDPC Decoding Architecture using Reweighted Offset Min-Sum Algorithm. - Sangbu Yun; Dongyun Kam; Jeongwon Choe; Byeong Yong Kong; Youngjoo Lee (ISCAS, 2020)

Retrain-Less Weight Quantization for Multiplier-Less Convolutional Neural Networks. - Jaewoong Choi; Byeong Yong Kong; In-Cheol Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

A Low-Latency Multi-Touch Detector Based on Concurrent Processing of Redesigned Overlap Split and Connected Component Analysis. - Byeong Yong Kong; Jooseung Lee; In-Cheol Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

A 120-mW 0.16-ms-Latency Connectivity-Scalable Multiuser Detector for Interleave Division Multiple Access. - Byeong Yong Kong; In-Cheol Park (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Low-Latency Polar Decoder Using Overlapped SCL Processing. - Dongyun Kam; Byeong Yong Kong; Youngjoo Lee (ICASSP, 2021)

Bitwise Early Termination of Multiuser Detection for IDMA Systems. - Byeong Yong Kong (IEEE Commun. Lett., 2021)

Real-Time SSDLite Object Detection on FPGA. - Suchang Kim; Seungho Na; Byeong Yong Kong; Jaewoong Choi; In-Cheol Park (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A 1.1μs 1.56Gb/s/mm2 Cost-Efficient Large-List SCL Polar Decoder Using Fully-Reusable LLR Buffers in 28nm CMOS Technology. - Dongyun Kam; Byeong Yong Kong; Youngjoo Lee (VLSI Technology and Circuits, 2022)

A 97-mW Bitwise-Early-Terminating Multiuser Detector for IDMA Systems. - Byeong Yong Kong (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Area- and Energy-Efficient LDPC Decoder Using Mixed-Resolution Check-Node Processing. - Sangbu Yun; Byeong Yong Kong; Youngjoo Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

An Automated Synthesis Framework for Fast Evaluation of Maximum Operating Frequency. - Byeong Yong Kong; Hoyoung Yoo; Youngjoo Lee (ICEIC, 2023)

Low-Latency SCL Polar Decoder Architecture Using Overlapped Pruning Operations. - Dongyun Kam; Byeong Yong Kong; Youngjoo Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Statistical Analysis of Bitwise Early Termination for Iterative Multiuser Detection in IDMA Systems. - Byeong Yong Kong (ICEIC, 2024)

Constrained Sorter Design using Zero-One Principle. - Sangil Han; Jaehee Kim; Dongyun Kam; Byeong Yong Kong; Mijung Kim; Young-Seok Kim; Youngjoo Lee (ISCAS, 2024)

A Design Framework for Cost-Efficient Sorters With Arbitrary Input/Output Constraints. - Jaehee Kim; Sangil Han; Dongyun Kam; Byeong Yong Kong; Youngjoo Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Low-Latency PAPR Reduction Architecture for Discrete Multitone Based on Approximate Midrange. - Byeong Yong Kong (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Scalable VLSI Architectures for Pattern Matching in Serial Data Stream. - Byeong Yong Kong (ICEIC, 2025)

Generalized Shifting-Based PAPR Reduction Architecture for Discrete Multitone Systems. - Byeong Yong Kong (ISCAS, 2025)