A 639.38GOPS Hybrid-Domain Logic-Compatible Multi-Level Embedded Flash Computing-in-Memory Macro with Spike-Edge Computation. - Jiho Chun; Edward Jongyoon Choi; Byeongseon Choi; Donghyeon Yi; Sohmyung Ha; Ik-Joon Chang; Minkyu Je (A-SSCC, 2024)

An SRAM-based Error-Free Time Domain Pulse Train Computing-In-Memory Macro achieving 226.14 TOPS/W and 5.782 TOPS/mm2. - Edward Jongyoon Choi; Jiho Chun; Byeongseon Choi; Sohmyung Ha; Ik-Joon Chang; Minkyu Je (ISOCC, 2024)