Leveraging designer's intent: A path toward simpler analog CAD tools. - Jaeha Kim; Metha Jeeradit; ByongChan Lim; Mark A. Horowitz (CICC, 2009)

Fortifying analog models with equivalence checking and coverage analysis. - Mark Horowitz; Metha Jeeradit; Frances Lau; Sabrina Liao; ByongChan Lim; James Mao (DAC, 2010)

An efficient test vector generation for checking analog/mixed-signal functional models. - ByongChan Lim; Jaeha Kim; Mark A. Horowitz (DAC, 2010)

Digital Analog Design: Enabling Mixed-Signal System Validation. - ByongChan Lim; Ji-Eun Jang; James Mao; Jaeha Kim; Mark Horowitz (IEEE Des. Test, 2015)

A 220pJ/pixel/frame CMOS image sensor with partial settling readout architecture. - Suyao Ji; Jing Pu; ByongChan Lim; Mark Horowitz (VLSI Circuits, 2016)

Error Control and Limit Cycle Elimination in Event-Driven Piecewise Linear Analog Functional Models. - ByongChan Lim; Mark Horowitz (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Fast FPGA emulation of analog dynamics in digitally-driven systems. - Steven Herbst; ByongChan Lim; Mark Horowitz (ICCAD, 2018)

An Analog Model Template Library: Simplifying Chip-Level, Mixed-Signal Design Verification. - ByongChan Lim; Mark Horowitz (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Open-Source Synthesizable Analog Blocks for High-Speed Link Designs: 20-GS/s 5b ENOB Analog-to-Digital Converter and 5-GHz Phase Interpolator. - Sung-Jin Kim; Zachary A. Myers; Steven Herbst; ByongChan Lim; Mark Horowitz (VLSI Circuits, 2020)