A 0.25-µm CMOS 1.9-GHz PHS RF Transceiver With a 150-kHz Low-IF Architecture. - Hoesam Jeong; Byoung-Joo Yoo; Cheol Kyu Han; Sang-Yoon Lee 006; Kang-Yoon Lee; Suhwan Kim 001; Deog-Kyoon Jeong; Wonchan Kim (IEEE J. Solid State Circuits, 2007)

250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 μ m CMOS. - Sang-Yoon Lee; Hyung-Rok Lee; Young-Ho Kwak; Woo-Seok Choi; Byoung-Joo Yoo; Daeyun Shim; Chulwoo Kim; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2011)

A model-first design and verification flow for analog-digital convergence systems: A high-speed receiver example in digital TVs. - Jaeha Kim; Sigang Ryu; Byoung-Joo Yoo; Hanseok Kim; Yunju Choi; Deog-Kyoon Jeong (ISCAS, 2012)

Design of CMOS 5 Gb/s 4-PAM transceiver frontend for low-power memory interface. - Woo-Rham Bae; Byoung-Joo Yoo; Deog-Kyoon Jeong (ISOCC, 2012)

A design of an area-efficient 10-GHz phase-locked loop for source-synchronous, multi-channel links in 90-nm CMOS technology. - Woo-Rham Bae; Deog-Kyoon Jeong; Byoung-Joo Yoo (DDECS, 2014)

Linearization Technique for Binary Phase Detectors in a Collaborative Timing Recovery Circuit. - Byoung-Joo Yoo; Woo-Rham Bae; Jiho Han; Jaeha Kim; Deog-Kyoon Jeong (IEEE Trans. Very Large Scale Integr. Syst., 2014)

6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier. - Byoung-Joo Yoo; Dong-Hyuk Lim; Hyonguk Pang; June-Hee Lee; Seung-Yeob Baek 002; Naxin Kim; Dong-Ho Choi; Young-Ho Choi; Hyeyeon Yang; Taehun Yoon; Sang-Hyeok Chu; Kangjik Kim; et al. (ISSCC, 2020)

A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links. - Timothy O. Dickson; Zeynep Toprak Deniz; Martin Cochet; Marcel A. Kossel; Thomas Morf; Young-Ho Choi; Pier Andrea Francese; Matthias Brändli; Troy J. Beukema; Christian W. Baks; Jonathan E. Proesel; John F. Bulzacchelli; et al. (VLSI Technology and Circuits, 2022)

An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS. - Serdar S. Yonar; Pier Andrea Francese; Matthias Brändli; Marcel A. Kossel; Thomas Morf; Jonathan E. Proesel; Sergey V. Rylov; Herschel A. Ainspan; Martin Cochet; Zeynep Toprak Deniz; Timothy O. Dickson; Troy J. Beukema; et al. (VLSI Technology and Circuits, 2022)

A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques. - Kihwan Seong; Donguk Park; Gyeom-Je Bae; Hyunwoo Lee; Youngseob Suh; Wooseuk Oh; Hyemun Lee; Juyoung Kim; Takgun Lee; Geonhoo Mo; Sukhyun Jung; Dongcheol Choi; et al. (ISSCC, 2023)

A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links. - Timothy O. Dickson; Zeynep Toprak Deniz; Martin Cochet; Troy J. Beukema; Marcel A. Kossel; Thomas Morf; Young-Ho Choi; Pier Andrea Francese; Matthias Brändli; Christian W. Baks; Jonathan E. Proesel; John F. Bulzacchelli; et al. (IEEE J. Solid State Circuits, 2023)

13.10 A 4nm 48Gb/s/wire Single-Ended NRZ Parallel Transceiver with Offset-Calibration and Equalization Schemes for Next-Generation Memory Interfaces and Chiplets. - Kihwan Seong; Wooseuk Oh; Hyunwoo Lee; Gyeom-Je Bae; Youngseob Suh; Hyemun Lee; Juyoung Kim; Eunsu Kim; Yeongeon Kang; Gunhu Mo; Youjin Lee; Mingyeong Kim; et al. (ISSCC, 2024)

How Effective are Large Language Models in Generating Software Specifications? - Danning Xie; Byoung-Joo Yoo; Nan Jiang 012; Mijung Kim; Lin Tan 001; Xiangyu Zhang 001; Judy S. Lee (SANER, 2025)