Current-voltage characteristics of vertical diodes for next generation memories. - Hokyun An; Kong-Soo Lee; Yoongoo Kang; Seonghoon Jeong; Wonseok Yoo; Jae-Jong Han; Bonghyun Kim; Hanjin Lim; Seokwoo Nam; Gi-Tae Jeong; Ho-Kyu Kang; Chilhee Chung; et al. (ESSDERC, 2012)

The effect of gate overlap lightly doped drains on low temperature poly-Si thin film transistors. - Jaehyun Cho; Sungwook Jung; Kyungsoo Jang; Hyungsik Park; Jongkyu Heo; Wonbaek Lee; DaeYoung Gong; Seungman Park; Hyungwook Choi; Hanwook Jung; Byoungdeog Choi; Junsin Yi (Microelectron. Reliab., 2012)

Novel Method for Nondestructive Body Effect Measurement in Dynamic Random Access Memory. - Il-Woo Jung; Bonggu Sung; Byoungdeog Choi (J. Electron. Test., 2017)

Novel Dual Work Function Buried Channel Array Transistor Process Design for Sub-17 nm DRAM. - Dong-Sik Park; Dong-Hyun Im; Yun-Jung Kim; Sung Sam Lee; Byung-Jae Kang; Jae-Hong Seo; Taewoong Koo; Byoungdeog Choi (IEEE Access, 2024)

Novel STI Technology for Enhancing Reliability of High-k/Metal Gate DRAM. - Hyojin Park; Gyuhyun Kil; Wonju Sung; Junghoon Han; Jungwoo Song; Byoungdeog Choi (IEEE Access, 2024)

String-level compact modeling of erase operations in the body-floated vertical channel of 3D charge trapping flash memory. - Sunghwan Cho; Byoungdeog Choi (Microelectron. J., 2024)

Suppression of Capacitor Leakage Through Thermal Budget Control in DRAM With ZrO2-Based Dielectrics. - Dong-Sik Park; Eun-Ok Lee; Jong-Min Lee; Eunae Cho; Byoungdeog Choi (IEEE Access, 2025)