A ROM compression method for continuous data. - Byung-Do Yang; Lee-Sup Kim (CICC, 2002)

A high speed direct digital frequency synthesizer using a low power pipelined parallel accumulator. - Byung-Do Yang; Lee-Sup Kim; Hyun-Kyu Yu (ISCAS (5), 2002)

A low power charge sharing ROM using dummy bit lines. - Byung-Do Yang; Lee-Sup Kim (ISCAS (5), 2003)

A low-power ROM using charge recycling and charge sharing techniques. - Byung-Do Yang; Lee-Sup Kim (IEEE J. Solid State Circuits, 2003)

A low-power charge-recycling ROM architecture. - Byung-Do Yang; Lee-Sup Kim (IEEE Trans. Very Large Scale Integr. Syst., 2003)

An error pattern ROM compression method for continuous data. - Byung-Do Yang; Lee-Sup Kim (ISCAS (2), 2004)

An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/a converter. - Byung-Do Yang; Jang-Hong Choi; Seon-Ho Han; Lee-Sup Kim; Hyun-Kyu Yu (IEEE J. Solid State Circuits, 2004)

A low-power SRAM using hierarchical bit line and local sense amplifiers. - Byung-Do Yang; Lee-Sup Kim (IEEE J. Solid State Circuits, 2005)

A low-power CAM using pulsed NAND-NOR match-line and charge-recycling search-line driver. - Byung-Do Yang; Lee-Sup Kim (IEEE J. Solid State Circuits, 2005)

A low-power ROM using single charge-sharing capacitor and hierarchical bit line. - Byung-Do Yang; Lee-Sup Kim (IEEE Trans. Very Large Scale Integr. Syst., 2006)

A Low Power Phase-Change Random Access Memory using a Data-Comparison Write Scheme. - Byung-Do Yang; Jae-Eun Lee; Jang-Su Kim; Junghyun Cho; Seung-Yun Lee; Byoung-Gon Yu (ISCAS, 2007)

A highly accurate BiCMOS cascode current mirror for wide output voltage range. - Byung-Do Yang; Jang-Su Kim; Jin-Kuk Yun; Yong-Kyu Lee; Jee-Sue Lee (ISCAS, 2008)

A Fast-switching Current-pulse Driver for LED Backlight. - Jang-Su Kim; Yong-Kyu Lee; Jee-Sue Lee; Young-Kyu Shin; Jung-Hyun Tark; Keun-Chul Ryu; Byung-Do Yang (ISCAS, 2009)

A Low-Power SRAM Using Bit-Line Charge-Recycling for Read and Write Operations. - Byung-Do Yang (IEEE J. Solid State Circuits, 2010)

A High-Efficiency On-Chip DC-DC Down-Conversion Using Selectable Supply-Voltage Charge-Recycling. - Byung-Do Yang (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Area-Efficient Prefilter Architecture for a CDMA Receiver. - Hyeong-Ju Kang; Seung Jae Lee 001; Byung-Do Yang (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A Low Power Content Addressable Memory Using Low Swing Search Lines. - Byung-Do Yang; Yong-Kyu Lee; Si-Woo Sung; Jae-Joong Min; Jae-Mun Oh; Hyeong-Ju Kang (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Low-Power Time Deinterleaver for ISDB-T Receiver. - Hyeong-Ju Kang; Byung-Do Yang (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

250-mV Supply Subthreshold CMOS Voltage Reference Using a Low-Voltage Comparator and a Charge-Pump Circuit. - Byung-Do Yang (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Low-Power Effective Memory-Size Expanded TCAM Using Data-Relocation Scheme. - Byung-Do Yang (IEEE J. Solid State Circuits, 2015)

Low-Power and Area-Efficient Shift Register Using Pulsed Latches. - Byung-Do Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Extracting the Source Code Context to Predict Import Changes using GPES. - Jaekwon Lee; Kisub Kim; Yonghyeon Lee; Jang-Eui Hong; Young-Hoon Seo; Byung-Do Yang; Woosung Jung (KSII Trans. Internet Inf. Syst., 2017)

Low-Area TCAM Using A Don't Care Reduction Scheme. - Ki-Chan Woo; Byung-Do Yang (IEEE J. Solid State Circuits, 2018)

Low Power Digital PWM Buck Converter With a Clock-Gating Shift-Register. - Tae-Hyeong Kim; Dae-Jin Kim; Hyeon-Sam Shin; Sang-Ho Lee; Jae-Won Suh; Byung-Do Yang (ICEIC, 2019)

A Voltage-Mode Buck Converter With a Reduced Type-I Compensation Capacitor Using an Error-Amplifier Current-Sampling Scheme. - Dae-Jin Kim; Tae-Hyeong Kim; Hyeon-Sam Shin; Bo-Seok Seo; Mi-Jeong Kim; Byung-Do Yang (ICEIC, 2019)

Depth Map Estimation Model with Efficient Feature Extraction Module. - Soo-Yeon Shin; Dong-Myung Kim; Byung-Do Yang; Chansik Park; Jae-Won Suh (ICEIC, 2019)

Area-Efficient Bidirectional Shift-Register Using Bidirectional Pulsed-Latches. - Ki-Chan Woo; Hyeong-Ju Kang; Byung-Do Yang (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

DC-DC Buck Converter Using Analog Coarse-Fine Self-Tracking Zero-Current Detection Scheme. - Ki-Chan Woo; Jae-Mun Oh; Byung-Do Yang (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Zinc Tin Oxide Synaptic Device for Neuromorphic Engineering. - Ji-Ho Ryu; Boram Kim; Fayyaz Hussain; Muhammad Ismail; Chandreswar Mahata; Teresa Oh; Muhammad Imran; Kyung Kyu Min; Tae-Hyeon Kim; Byung-Do Yang; Seongjae Cho; Byung-Gook Park; et al. (IEEE Access, 2020)

Low-Area and Low-Power Latch-Based Thermometer-Code Shift-Register. - Ki-Chan Woo; Hyeong-Ju Kang; Byung-Do Yang (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

0.3-V RC-to-Digital Converter Using a Negative Charge-Pump Switch. - Ki-Chan Woo; Byung-Do Yang (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 0.25-V Rail-to-Rail Three-Stage OTA With an Enhanced DC Gain. - Ki-Chan Woo; Byung-Do Yang (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 0.35V 90nA Quiescent Current Output-Capacitor-Less NMOS Low-Dropout Regulator Using a Coarse-Fine Charge-Pump Circuit. - Ki-Chan Woo; Byung-Do Yang (IEEE Trans. Circuits Syst., 2020)

AoCStream: All-on-Chip CNN Accelerator with Stream-Based Line-Buffer Architecture and Accelerator-Aware Pruning. - Hyeong-Ju Kang; Byung-Do Yang (Sensors, 2023)