Timing driven force-directed floorplanning with incremental static timing analyzer. - Sea-Ho Kim; Byung-Gyu Ahn; Ki-Seok Chung; Sung-Hwan Oh (APCCAS, 2008)

Power-Aware Test Framework for Network-on-Chip. - Byung-Gyu Ahn; Jun-Mo Jung; Jong-Wha Chong (ICONS, 2008)

Chart Pruning for Fast Lexicalised-Grammar Parsing. - Yue Zhang 004; Byung-Gyu Ahn; Stephen Clark; Curt Van Wyk; James R. Curran; Laura Rimell (COLING (Posters), 2010)

The Machine Translation Toolpack for LoonyBin: Automated Management of Experimental Machine Translation HyperWorkflows. - Jonathan H. Clark; Jonathan Weese; Byung-Gyu Ahn; Andreas Zollmann; Qin Gao; Kenneth Heafield; Alon Lavie (Prague Bull. Math. Linguistics, 2010)

Thermal aware timing budget for buffer insertion in early stage of physical design. - Minbeom Kim; Byung-Gyu Ahn; Jaehwan Kim; Bongki Lee; Jong-Wha Chong (ISCAS, 2012)

A novel methodology for power delivery network optimization in 3-D ICs using through-silicon-via technology. - Bongki Lee; Byung-Gyu Ahn; Jaehwan Kim; Minbeom Kim; Jong-Wha Chong (ISCAS, 2012)

Learning Non-linear Features for Machine Translation Using Gradient Boosting Machines. - Kristina Toutanova; Byung-Gyu Ahn (ACL (2), 2013)

Power bumps and through-silicon-vias placement with optimised power mesh structure for power delivery network in three-dimensional-integrated circuits. - Cheoljon Jang; Jaehwan Kim; Byung-Gyu Ahn; Jongwha Chong (IET Comput. Digit. Tech., 2013)