1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture. - Yongsam Moon; Yong-Ho Cho; Hyun-Bae Lee; Byung-Hoon Jeong; Seok-Hun Hyun; Byungchul Kim; In-Chul Jeong; Seong-Young Seo; Junho Shin; Seok-Woo Choi; Ho-Sung Song; Jung-Hwan Choi; et al. (ISSCC, 2009)

A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW. - Hoeju Chung; Byung-Hoon Jeong; ByungJun Min; Youngdon Choi; Beak-Hyung Cho; Junho Shin; Jinyoung Kim; Jung Sunwoo; Joon-min Park; Qi Wang; Yong-jun Lee; Sooho Cha; et al. (ISSCC, 2011)