A low power discrete-time receiver for triple-band FM/T-DMB/DAB system-on-chip. - Hoai-Nam Nguyen; Seung-Hwan Jung; Byung-Hun Min; Young-Jae Lee; Sang-Gug Lee 001; Yun Seong Eo; Hyun-Kyu Yu (ESSCIRC, 2011)

A 4-GHz All Digital PLL With Low-Power TDC and Phase-Error Compensation. - Ja-Yol Lee; Mi-Jeong Park; Byung-Hun Min; Seongdo Kim; Mun-Yang Park; Hyun-Kyu Yu (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

1-5.6 Gb/s CMOS clock and data recovery IC with a static phase offset compensated linear phase detector. - Sangjin Byun; Chung Hwan Son; Jongil Hwang; Byung-Hun Min; Mun-Yang Park; Hyun-Kyu Yu (IET Circuits Devices Syst., 2013)