A 1.2V 64Gb 341GB/S HBM2 stacked DRAM with spiral point-to-point TSV structure and improved bank group data control. - Jin-Hee Cho; Jihwan Kim; Wooyoung Lee; Dong-Uk Lee; Tae-Kyun Kim 002; Heat Bit Park; Chunseok Jeong; Myeong-Jae Park; Seung Geun Baek; Seokwoo Choi; Byung Kuk Yoon; Young Jae Choi; et al. (ISSCC, 2018)

A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization. - Myeong-Jae Park; Ho Sung Cho; Tae-Sik Yun; Sangjin Byeon; Young Jun Koo; Sang-Sic Yoon; Dong-Uk Lee; Seokwoo Choi; Ji Hwan Park; Jinhyung Lee; Kyungjun Cho; Junil Moon; et al. (ISSCC, 2022)

A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization. - Myeong-Jae Park; Jinhyung Lee; Kyungjun Cho; Ji Hwan Park; Junil Moon; Sung-Hak Lee; Tae-Kyun Kim 001; Sanghoon Oh; Seokwoo Choi; Yongsuk Choi; Ho Sung Cho; Tae-Sik Yun; et al. (IEEE J. Solid State Circuits, 2023)