A highly reliable multi-cell antifuse scheme using DRAM cell capacitors. - Jong-Pil Son; Jin Ho Kim; Woo Song Ahn; Seung Uk Han; Byung-Sick Moon; Churoo Park; Hong-Sun Hwang; Seong-Jin Jang; Joo-Sun Choi; Young-Hyun Jun; Soo-Won Kim (ESSCIRC, 2010)

An Area-Efficient, Low-VDD, Highly Reliable Multi-Cell Antifuse System Fully Operative in DRAMs. - Jong-Pil Son; Jin Ho Kim; Woo Song Ahn; Seung Uk Han; Satoru Yamada; Byung-Sick Moon; Churoo Park; Hong-Sun Hwang; Seong-Jin Jang; Joo-Sun Choi; Young-Hyun Jun; Soo-Won Kim (IEICE Trans. Electron., 2011)

A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme. - Kyomin Sohn; Taesik Na; Indal Song; Yong Shim; Wonil Bae; Sanghee Kang; Dongsu Lee; Hangyun Jung; Hanki Jeoung; Ki Won Lee; Junsuk Park; Jongeun Lee; et al. (ISSCC, 2012)