A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth. - Jei-Hwan Yoo; Chang-Hyun Kim; Kyu-Chan Lee; Kye-Hyun Kyung; Seung-Moon Yoo; Jung-Hwa Lee; Moon-Hae Son; Jin-Man Han; Bok-Moon Kang; Ejaz Haq; Sang-Bo Lee; Jai-Hoon Sim; et al. (IEEE J. Solid State Circuits, 1996)

Low-voltage, high-speed circuit designs for gigabit DRAMs. - Kyu-Chan Lee; Changhyun Kim; Dong-Ryul Ryu; Jai-Hoon Sim; Sang-Bo Lee; Byung-Sik Moon; Keum-Yong Kim; Nam-Jong Kim; Seung-Moon Yoo; Hongil Yoon; Jei-Hwan Yoo; Soo-In Cho (IEEE J. Solid State Circuits, 1997)

A 1 Gbit synchronous dynamic random access memory with an independent subarray-controlled scheme and a hierarchical decoding scheme. - Kyu-Chan Lee; Changhyun Kim; Hongil Yoon; Keum-Yong Kim; Byung-Sik Moon; Sang-Bo Lee; Jung-Hwa Lee; Nam-Jong Kim; Soo-In Cho (IEEE J. Solid State Circuits, 1998)

A 2.5-V, 72-Mbit, 2.0-GByte/s packet-based DRAM with a 1.0-Gbps/pin interface. - Changhyun Kim; Kye-Hyun Kyung; W.-P. Jeong; J.-S. Kim; Byung-Sik Moon; Joon-Wan Chai; S.-M. Yim; Jung-Hwan Choi; K.-H. Han; C.-J. Park; Hong-Sun Hwang; H. Choi; et al. (IEEE J. Solid State Circuits, 1999)