A 1.2V 23nm 6F2 4Gb DDR3 SDRAM with local-bitline sense amplifier, hybrid LIO sense amplifier and dummy-less array architecture. - Kyu-Nam Lim; Woong-Ju Jang; Hyung-Sik Won; Kang-Yeol Lee; Hyungsoo Kim; Dong-Whee Kim; Mi-Hyun Cho; Seung-Lo Kim; Jong-Ho Kang; Keun-Woo Park; Byung-Tae Jeong (ISSCC, 2012)