Efficient Data Transmission Scheme among Multi-devices. - Sang-Bong Byun; Byungin Moon; Yong-Hwan Lee (FGIT-FGCN, 2009)

A Fully Parallel, High-Speed BPC Hardware Architecture for the EBCOT in JPEG 2000. - Dong-Hwi Woo; Kyeong-Ryeol Bae; Hyeon-Sik Son; Seung-Ho Ok; Yong-Hwan Lee; Byungin Moon (FGIT-FGCN (2), 2010)

An Efficient Interworking Architecture of a Network Processor for Layer 7 Packet Processing. - Kyeong-Ryeol Bae; Seung-Ho Ok; Hyeon-Sik Son; Sang Yoon Oh; Yong-Hwan Lee; Byungin Moon (FGIT-FGCN (1), 2011)

A Platform for Real Time Brain-Waves Analysis System. - Eun-Gyu Jeong; Byungin Moon; Yong-Hwan Lee (FGIT-GDC, 2011)

Hardware Architecture of Bilateral Filter to Remove Haze. - Eun-Kyoung Kim; Jae-Dong Lee; Byungin Moon; Yong-Hwan Lee (FGIT-FGCN (1), 2011)

A Rectification Hardware Architecture for an Adaptive Multiple-Baseline Stereo Vision System. - Hyeon-Sik Son; Kyeong-Ryeol Bae; Seung-Ho Ok; Yong-Hwan Lee; Byungin Moon (FGIT-FGCN (1), 2011)

Design and analysis of 3D IC-based low power stereo matching processors. - Seung-Ho Ok; Kyeong-Ryeol Bae; Sung Kyu Lim; Byungin Moon (ISLPED, 2013)

A census-based stereo matching algorithm with multiple sparse windows. - Kyeong-Ryeol Bae; Hyeon-Sik Son; Jongkil Hyun; Byungin Moon (ICUFN, 2015)

A Multi-Level Accumulation-Based Rectification Method and Its Circuit Implementation. - Hyeon-Sik Son; Byungin Moon (KSII Trans. Internet Inf. Syst., 2017)

An Improved Stereo Matching Algorithm with Robustness to Noise Based on Adaptive Support Weight. - Ingyu Lee; Byungin Moon (J. Inf. Process. Syst., 2017)

An accurate and cost-effective stereo matching algorithm and processor for real-time embedded multimedia systems. - Kyeong-Ryeol Bae; Byungin Moon (Multim. Tools Appl., 2017)

A simplified rectification method and its hardware architecture for embedded multimedia systems. - Jongkil Hyun; Byungin Moon (Multim. Tools Appl., 2017)

A study of partitioned DIMM tree management for multimedia server systems. - Young-Kyu Kim; Yong-Hwan Lee; Byungin Moon (Multim. Tools Appl., 2017)

The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors. - Seung-Ho Ok; Yong-Hwan Lee; Jae Hoon Shim; Sung Kyu Lim; Byungin Moon (Sensors, 2017)

Drivable Area Detection Method Capable of Distinguishing Vegetation Area on Country Road. - Sangjae Lee; Byungin Moon (ISOCC, 2018)

3D die-stacked DRAM thermal management via task allocation and core pipeline control. - Changho Yoon; Jae Hoon Shim; Byungin Moon; Joonho Kong (IEICE Electron. Express, 2018)

Modified adaptive support weight and disparity search range estimation schemes for stereo matching processors. - Seung-Ho Ok; Jae Hoon Shim; Byungin Moon (J. Supercomput., 2018)

Cache memory organization for processing in memory. - Young-Kyu Kim; Byungin Moon; Dong-Sun Kim; Young-Jong Jang (IEICE Electron. Express, 2019)

Low-cost Hardware Architecture for Integral Image Generation using Word Length Reduction. - Junghwan Kim; Jongkil Hyun; Byungin Moon (ISOCC, 2020)

Hardware Architecture of a Haar Classifier Based Face Detection System Using a Skip Scheme. - Jongkil Hyun; Junghwan Kim; Cheol-Ho Choi; Byungin Moon (ISCAS, 2021)

Haar Filter Hardware Architecture for the Accuracy Improvement of Stereo Vision Systems. - Cheol-Ho Choi; Younghyeon Kim; Jiseok Ha; Byungin Moon (ISOCC, 2021)

A Haar Classifier Accelerator with Reduced Multiplexer Usage. - SangHyun Lee; Byungin Moon (ISOCC, 2021)

Hardware-friendly architecture for a pseudo 2D weighted median filter based on sparse-window approach. - Jongkil Hyun; Younghyeon Kim; Junghwan Kim; Byungin Moon (Multim. Tools Appl., 2021)