Control of a dual stage actuator system for noncircular cam turning process. - Byungsub Kim; Hanwu Li; Tsu-Chin Tsao (ACC, 2001)

Robust repetitive controller design with improved performance. - Byungsub Kim; Tsu-Chin Tsao (ACC, 2001)

Power-adaptive operational amplifier with positive-feedback self biasing. - Byungsub Kim; Soumyajit Mandal; Rahul Sarpeshkar (ISCAS, 2006)

Equalized interconnects for on-chip networks: modeling and optimization framework. - Byungsub Kim; Vladimir Stojanovic (ICCAD, 2007)

Characterization of Equalized and Repeated Interconnects for NoC Applications. - Byungsub Kim; Vladimir Stojanovic (IEEE Des. Test Comput., 2008)

Designing Energy-Efficient Low-Diameter On-Chip Networks with Equalized Interconnects. - Ajay Joshi; Byungsub Kim; Vladimir Stojanovic (Hot Interconnects, 2009)

A 4Gb/s/ch 356fJ/b 10mm equalized on-chip interconnect with nonlinear charge-injecting transmit filter and transimpedance receiver in 90nm CMOS. - Byungsub Kim; Vladimir Stojanovic (ISSCC, 2009)

A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS. - Yong Liu 023; Byungsub Kim; Timothy O. Dickson; John F. Bulzacchelli; Daniel J. Friedman (ISSCC, 2009)

A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS. - Byungsub Kim; Yong Liu 023; Timothy O. Dickson; John F. Bulzacchelli; Daniel J. Friedman (IEEE J. Solid State Circuits, 2009)

Precision Component Technologies for Microfactory Systems Developed at KIMM. - Jong-Kweon Park; Seung-Kook Ro; Byungsub Kim; Woo Cheol Shin; Hyeon-Hwa Lee (Int. J. Autom. Technol., 2010)

An Energy-Efficient Equalized Transceiver for RC-Dominant Channels. - Byungsub Kim; Vladimir Stojanovic (IEEE J. Solid State Circuits, 2010)

Equalized on-chip interconnect: modeling, analysis, and design. - Byungsub Kim (2010)

A 1.9-GHz Fractional-N Digital PLL With Subexponent ΔΣ TDC and IIR-Based Noise Cancellation. - Dong-Woo Jee; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A FIR-Embedded Phase Interpolator Based Noise Filtering for Wide-Bandwidth Fractional-N PLL. - Dong-Woo Jee; Yunjae Suh; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2013)

A 5 Gb/s Single-Ended Parallel Receiver With Adaptive Crosstalk-Induced Jitter Cancellation. - Seon-Kyoo Lee; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2013)

A QDR-Based 6-GB/s Parallel Transceiver With Current-Regulated Voltage-Mode Output Driver and Byte CDR for Memory Interface. - Seon-Kyoo Lee; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A 10-bit 25-MS/s 1.25-mW Pipelined ADC With a Semidigital Gm-Based Amplifier. - Yunjae Suh; Jongmi Lee; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A voltage-scalable 10-b pipelined ADC with current-mode amplifier. - Yunjae Suh; Seungnam Choi; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (CICC, 2014)

A 0.4 V driving multi-touch capacitive sensor with the driving signal frequency set to (n+0.5) times the inverse of the LCD VCOM noise period. - Jae-Seung Lee; Dong-Hee Yeo; Sang-Soo Lee; Hye-Jung Kwon; Jae-Yoon Sim; Byungsub Kim; Hong-June Park (ISCAS, 2014)

2.6 A 5.67mW 9Gb/s DLL-based reference-less CDR with pattern-dependent clock-embedded signaling for intra-panel interface. - Dong Hoon Baek; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (ISSCC, 2014)

2.7 A coefficient-error-robust FFE TX with 230% eye-variation improvement without calibration in 65nm CMOS technology. - Seungho Han; Sooeun Lee; Minsoo Choi 002; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (ISSCC, 2014)

24.8 An analog-digital-hybrid single-chip RX beamformer with non-uniform sampling for 2D-CMUT ultrasound imaging to achieve wide dynamic range of delay and small chip area. - Ji-Yong Um; Eun-Woo Song; Yoon-Jee Kim; Seong-Eun Cho; Min-Kyun Chae; Jongkeun Song; Bae-Hyung Kim; Seunghun Lee; Jihoon Bang; Youngil Kim; Kyungil Cho; Byungsub Kim; et al. (ISSCC, 2014)

Current-Mode Transceiver for Silicon Interposer Channel. - Seung-Hun Lee; Seon-Kyoo Lee; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2014)

An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface. - Soo-Min Lee; Il-Min Yi; Hae-Kang Jung; Hyunbae Lee; Yong-Ju Kim; Yunsaing Kim; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE J. Solid State Circuits, 2014)

An Analog-Digital Hybrid RX Beamformer Chip With Non-Uniform Sampling for Ultrasound Medical Imaging With 2D CMUT Array. - Ji-Yong Um; Yoon-Jee Kim; Seong-Eun Cho; Min-Kyun Chae; Jongkeun Song; Bae-Hyung Kim; Seung-Hun Lee; Jihoon Bang; Youngil Kim; Kyungil Cho; Byungsub Kim; Jae-Yoon Sim; et al. (IEEE Trans. Biomed. Circuits Syst., 2014)

An Approximate Closed-Form Channel Model for Diverse Interconnect Applications. - Minsoo Choi 002; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

A 0.5-V, 1.47- µW 40-kS/s 13-bit SAR ADC With Capacitor Error Compensation. - Hyunsoo Ha; Seon-Kyoo Lee; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Analysis of an Open-Loop Time Amplifier With a Time Gain Determined by the Ratio of Bias Current. - Hye-Jung Kwon; Jae-Seung Lee; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A 40-mV-Swing Single-Ended Transceiver for TSV with a Switched-Diode RX Termination. - Il-Min Yi; Soo-Min Lee; Seung-Jun Bae; Young-Soo Sohn; Jung-Hwan Choi; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A Sample Reduction Technique by Aliasing Channel Response for Fast Equalizing Transceiver Design. - Sooeun Lee; Gunbok Lee; Jae-Yoon Sim; Hong-June Park; Wee Sang Park; Byungsub Kim (ICCAD, 2015)

5.7 A 29nW bandgap reference circuit. - Jongmi Lee; Youngwoo Ji; Seungnam Choi; Young-Chul Cho; Seong-Jin Jang; Joo-Sun Choi; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (ISSCC, 2015)

An input pole tuned switching equalization scheme for high-speed serial links. - Sanquan Song; Jian Xu; Fengxiang Cai; Xin Ma; Zibing Yang; Matthew Becker; Larry Tate; Byungsub Kim; Samuel Palermo; William J. Bowhill (MWSCAS, 2015)

A Single-Chip 32-Channel Analog Beamformer With 4-ns Delay Resolution and 768-ns Maximum Delay Range for Ultrasound Medical Imaging With a Linear Array Transducer. - Ji-Yong Um; Yoon-Jee Kim; Seong-Eun Cho; Min-Kyun Chae; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Biomed. Circuits Syst., 2015)

An Approximate Closed-Form Transfer Function Model for Diverse Differential Interconnects. - Minsoo Choi 002; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A low-power LDO circuit with a fast load regulation. - Young Jae Jang; Seong-Eun Cho; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (APCCAS, 2016)

Read margin analysis in an ReRAM crossbar array. - JaeHyun Seo; Byungsub Kim (APCCAS, 2016)

All-synthesizable 6Gbps voltage-mode transmitter for serial link. - Young-Ho Choi; Kihwan Seong; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (A-SSCC, 2016)

All-synthesizable transmitter driver and data recovery circuit for USB2.0 interface. - Kihwan Seong; Won-Cheol Lee; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (ISOCC, 2016)

A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme. - Il-Min Yi; Seung-Jun Bae; Min-Kyun Chae; Soo-Min Lee; Young Jae Jang; Young-Chul Cho; Young-Soo Sohn; Jung-Hwan Choi; Seong-Jin Jang; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (VLSI Circuits, 2016)

A Coefficient-Error-Robust Feed-Forward Equalizing Transmitter for Eye-Variation and Power Improvement. - Seungho Han; Sooeun Lee; Minsoo Choi 002; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (IEEE J. Solid State Circuits, 2016)

A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC. - Shinwoong Kim; Seunghwan Hong; Kapseok Chang; Hyungsik Ju; Jaewook Shin; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2016)

A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface. - Soo-Min Lee; Ji-Hoon Lim; Il-Min Yi; Young Jae Jang; Hae-Kang Jung; Kyunghoon Kim; Dae-Han Kwon; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE J. Solid State Circuits, 2016)

A 0.65-to-10.5 Gb/s Reference-Less CDR With Asynchronous Baud-Rate Sampling for Frequency Acquisition and Adaptive Equalization. - Seungnam Choi; Hyunwoo Son; Jongshin Shin; Sang-Hyun Lee; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%-80% Input Duty Cycle for SDRAMs. - Ji-Hoon Lim; Jun-Hyun Bae; Jaemin Jang; Hae-Kang Jung; Hyunbae Lee; Yongju Kim; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s. - Il-Min Yi; Soo-Min Lee; Seung-Jun Bae; Young-Soo Sohn; Jung-Hwan Choi; Seong-Jin Jang; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

A 10-GHz multi-purpose reconfigurable built-in self-test circuit for high-speed links. - Myungguk Lee; Seungho Han; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (A-SSCC, 2017)

8.7 A 0.0047mm2 highly synthesizable TDC- and DCO-less fractional-N PLL with a seamless lock range of fREF to 1GHz. - Hwasuk Cho; Kihwan Seong; Kwang-Hee Choi; Jin-Hyeok Choi; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (ISSCC, 2017)

5.8 A 9.3nW all-in-one bandgap voltage and current reference circuit. - Youngwoo Ji; Cheonhoo Jeon; Hyunwoo Son; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (ISSCC, 2017)

5.5 A quadrature relaxation oscillator with a process-induced frequency-error compensation loop. - Jahyun Koo 001; Kyoung-Sik Moon; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (ISSCC, 2017)

23.7 A time-based receiver with 2-tap DFE for a 12Gb/s/pin single-ended transceiver of mobile DRAM interface in 0.8V 65nm CMOS. - Il-Min Yi; Min-Kyun Chae; Seok-Hun Hyun; Seung-Jun Bae; Jung-Hwan Choi; Seong-Jin Jang; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (ISSCC, 2017)

A Single-Chip 64-Channel Ultrasound RX-Beamformer Including Analog Front-End and an LUT for Non-Uniform ADC-Sample-Clock Generation. - Yoon-Jee Kim; Sung-Eun Cho; Ji-Yong Um; Min-Kyun Chae; Jihoon Bang; Jongkeun Song; Taeho Jeon; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Biomed. Circuits Syst., 2017)

A Low-Power Wide Dynamic-Range Current Readout Circuit for Ion-Sensitive FET Sensors. - Hyunwoo Son; Hwasuk Cho; Jahyun Koo 001; Youngwoo Ji; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Biomed. Circuits Syst., 2017)

A Phase-Interpolator-Based Fractional Counter for All-Digital Fractional-N Phase-Locked Loop. - Young-Ho Choi; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A Self-Biased Current-Mode Amplifier With an Application to 10-bit Pipeline ADC. - Seungnam Choi; Yunjae Suh; Joohyun Lee; Jinkyu Kim; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A 250-µW 2.4-GHz Fast-Lock Fractional-N Frequency Generation for Ultralow-Power Applications. - Seunghwan Hong; Shinwoong Kim; Seungnam Choi; Hwasuk Cho; Jaehyeong Hong; Young Hun Seo; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

An Approximate Transfer Function Model of Two Serially Connected Heterogeneous Transmission Lines. - Jaeyoung Seo; Minsoo Choi 002; Sanquan Song; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Automatic ReRAM SPICE Model Generation From Empirical Data for Fast ReRAM-Circuit Coevaluation. - JaeHyun Seo; Sangheon Lee; Kwangmin Kim; Sooeun Lee; Hyunsang Hwang; Byungsub Kim (IEEE Trans. Very Large Scale Integr. Syst., 2017)

All-Synthesizable Current-Mode Transmitter Driver for USB2.0 Interface. - Kihwan Seong; Won-Cheol Lee; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Investigation on the Worst Read Scenario of a ReRAM Crossbar Array. - Yelim Youn; Kwangmin Kim; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A 9.3 nW all-in-one bandgap voltage and current reference circuit using leakage-based PTAT generation and DIBL characteristic. - Youngwoo Ji; Cheonhoo Jeon; Hyunwoo Son; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (ASP-DAC, 2018)

A 16.6-pJ/b 150-Mb/s body-channel communication transceiver with decision feedback equalization improving >200x area efficiency. - Ji-Hoon Lee; Kwangmin Kim; Minsoo Choi 002; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (ASP-DAC, 2018)

A low-power wide dynamic-range current readout circuit for biosensors. - Hyunwoo Son; Hwasuk Cho; Jahyun Koo 001; Youngwoo Ji; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (ASP-DAC, 2018)

A 12-Gb/s AC-Coupled FFE TX With Adaptive Relaxed Impedance Matching Achieving Adaptation Range of 35-75Ω Z0 and 30-550Ω RRX. - Minsoo Choi 002; Myungguk Lee; Byungsub Kim (A-SSCC, 2018)

Experimental Verification of a Simple, Intuitive, and Accurate Closed-Form Transfer Function Model for Diverse High-Speed Interconnects. - Kyunghyun Lim; Minsoo Choi 002; Myat Thu Linn Aung; Kyunghwan Kim; Ji-Seong Kim; Rock-Hyun Baek; Ho-Jin Song; Tony Tae-Hyoung Kim; Byungsub Kim (ISOCC, 2018)

A Rule-of-thumb Condition to Avoid Large HRS Current in ReRAM Crossbar Array Design. - Yelim Youn; Kwangmin Kim; Byungsub Kim (ISOCC, 2018)

A 0.3-to-1.2V frequency-scalable fractional-N ADPLL with a speculative dual-referenced interpolating TDC. - Minseob Lee; Shinwoong Kim; Hwasuk Cho; Jahyun Koo 001; Kwang-Hee Choi; Jin-Hyeok Choi; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (ISSCC, 2018)

A 7.8Gb/s/pin 1.96pJ/b compact single-ended TRX and CDR with phase-difference modulation for highly reflective memory interfaces. - Sooeun Lee; Jaeyoung Seo; Kyunghyun Lim; Jaehyun Ko 001; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (ISSCC, 2018)

An 84.6-dB-SNDR and 98.2-dB-SFDR Residue-Integrated SAR ADC for Low-Power Sensor Applications. - Seungnam Choi; Hwan-Seok Ku; Hyunwoo Son; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2018)

An FFE Transmitter Which Automatically and Adaptively Relaxes Impedance Matching. - Minsoo Choi 002; Sooeun Lee; Myungguk Lee; Ji-Hoon Lee; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (IEEE J. Solid State Circuits, 2018)

A Time-Based Receiver With 2-Tap Decision Feedback Equalizer for Single-Ended Mobile DRAM Interface. - Il-Min Yi; Min-Kyun Chae; Seok-Hun Hyun; Seung-Jun Bae; Jung-Hwan Choi; Seong-Jin Jang; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE J. Solid State Circuits, 2018)

An On-Chip Learning Neuromorphic Autoencoder With Current-Mode Transposable Memory Read and Virtual Lookup Table. - Hwasuk Cho; Hyunwoo Son; Kihwan Seong; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Biomed. Circuits Syst., 2018)

An Approximate Closed-Form Transfer Function Model for Multiconductor Transmission Lines. - Jaeyoung Seo; Minsoo Choi 002; Byungsub Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Study on Bandgap Reference Circuit With Leakage-Based PTAT Generation. - Youngwoo Ji; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A Search Algorithm for the Worst Operation Scenario of a Cross-Point Phase-Change Memory Utilizing Particle Swarm Optimization. - Kwangmin Kim; Seokjoon Kang; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A 192pW Hybrid Bandgap-Vth Reference with Process Dependence Compensated by a Dimension-Induced Side-Effect. - Youngwoo Ji; Jungho Lee; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (ISSCC, 2019)

A 143nW Glucose-Monitoring Smart Contact Lens IC with a Dual-Mode Transmitter for Wireless-Powered Backscattering and RF-Radiated Transmission Using a Single Loop Antenna. - Cheonhoo Jeon; Jahyun Koo 001; Kyongsu Lee; Su-Kyoung Kim; Sei Kwang Hahn; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (VLSI Circuits, 2019)

A 192-pW Voltage Reference Generating Bandgap- $V_{ text{th}}$ With Process and Temperature Dependence Compensation. - Youngwoo Ji; Jungho Lee; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2019)

A Multilayer-Learning Current-Mode Neuromorphic System With Analog-Error Compensation. - Hyunwoo Son; Hwasuk Cho; Jungho Lee; Seongun Bae; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Biomed. Circuits Syst., 2019)

A Quadrature RC Oscillator With Noise Reduction by Voltage Swing Control. - Jahyun Koo 001; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Code Inversion Encoding Technique to Improve Read Margin of A Cross-Point Phase Change Memory. - Kwangmin Kim; Seokjoon Kang; Byungsub Kim (IEEE Trans. Very Large Scale Integr. Syst., 2019)

GUI-Enhanced Layout Generation of FFE SST TXs for Fast High-Speed Serial Link Design. - Seungho Han; Sungyu Jeong; Chanho Kim; Hong-June Park; Byungsub Kim (DAC, 2020)

A Body Channel Communication Technique Utilizing Decision Feedback Equalization. - Ji-Hoon Lee; Jaehyun Ko 001; Kwangmin Kim; Minsoo Choi 002; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (IEEE Access, 2020)

A pattern-dependent injection-locked CDR for clock-embedded signaling. - Jaehyeong Hong; Dong Hoon Baek; Hyunwoo Son; Cheolmin Ahn; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (Microelectron. J., 2020)

An 18-Gb/s NRZ Transceiver With a Channel-Included 2-UI Impulse-Response Filtering FFE and 1-Tap DFE Compensating up to 32-dB Loss. - Cheolmin Ahn; Jaehyeong Hong; Jongshin Shin; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Circuits Syst., 2020)

Low-Power Small-Area Inverter-Based DSM for MEMS Microphone. - Seong-Eun Cho; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst., 2020)

A 7.8 Gb/s/pin, 1.96 pJ/b Transceiver With Phase-Difference-Modulation Signaling for Highly Reflective Interconnects. - Sooeun Lee; Jaeyoung Seo; Kyunghyun Lim; Jahyun Koo 001; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

A 7.8-Gb/s 2.9-pJ/b Single-Ended Receiver With 20-Tap DFE for Highly Reflective Channels. - Jaeyoung Seo; Jaehyun Ko 001; Kyunghyun Lim; Sooeun Lee; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (IEEE Trans. Very Large Scale Integr. Syst., 2020)

The development of a micro-pattern manufacturing method using rotating active tools with compensation of estimated errors and an LMS algorithm. - Soo-Bong Cho; Seung-Kook Ro; Byungsub Kim; Sungcheul Lee; Jong-Kweon Park (J. Intell. Manuf., 2021)

A DFE-Enhanced Phase-Difference Modulation Signaling for Multi-Drop Memory Interfaces. - Sooeun Lee; Jaeyoung Seo; Changyoon Han; Jae-Yoon Sim; Hong-June Park; Byungsub Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A Study On Reliable High-Speed HBC Enhanced by ECC for Wearable Neural Interfaces. - Seungsik Moon; Jaehyun Ko 001; Byungsub Kim; Youngjoo Lee (AICAS, 2022)

A 50 Mb/s Full HBC TRX with Adaptive DFE and Variable-Interval 3x Oversampling CDR in 28nm CMOS Technology for A 75 cm Body Channel Moving at 0.75 Cycle/sec. - Jaehyun Ko 001; Iksu Jang; Chanho Kim; Jihoon Park; Changjae Moon; Sooeun Lee; Byungsub Kim (ESSCIRC, 2022)

A Layout Generator of Latch, Flip-Flop, and Shift Register for High-Speed Links. - Junung Choi; Jaeik Cho; Won Joon Choi; Myungguk Lee; Byungsub Kim (ISOCC, 2022)

A Cost-efficient FPGA-based Embedded System for Biosensor Platform. - Iksu Jang; Jaeyoung Seo; Changjae Moon; Byungsub Kim (ISOCC, 2022)

A Fast Eye Size Evaluation Method for High Speed Signal. - Hyoseok Song; Kwangmin Kim; Changyoon Han; Byungsub Kim (ISOCC, 2022)

A 20 Gb/s/pin 1.18pJ/b 1149µm2Single-Ended Inverter-based 4-tap Addition-Only Feed-Forward Equalization Transmitter with Improved Robustness to Coefficient Errors in 28nm CMOS. - Changjae Moon; Jaeyoung Seo; Myungguk Lee; Iksu Jang; Byungsub Kim (ISSCC, 2022)

A 20-Gb/s/pin 0.0024-mm2 Single-Ended DECS TRX with CDR-less Self-Slicing/Auto-Deserialization to Improve Tolerance on Duty Cycle Error and RX Supply Noise for DCC/CDR-less Short-Reach Memory Interfaces. - Jaeyoung Seo; Sooeun Lee; Myungguk Lee; Changjae Moon; Byungsub Kim (ISSCC, 2022)

A Compact Single-Ended Inverter-Based Transceiver With Swing Improvement for Short-Reach Links. - Myungguk Lee; Puneet Kanwar Kaur; Jaeyoung Seo; Seungho Han; Byungsub Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Review: A Speculative Divide-and-Conquer Optimization Method for Large Analog/Mixed-Signal Circuits. - Hyoseok Song; Kwangmin Kim; Changyoon Han; Byungsub Kim (ISOCC, 2023)

A Speculative Divide-and-Conquer Optimization Method for Large Analog/Mixed-Signal Circuits: A High-Speed FFE SST Transmitter Example. - Kwangmin Kim; Hyoseok Song; Byeongcheol Lee; Byungsub Kim (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A 20-Gb/s/Pin Compact Single-Ended DCC-Less DECS Transceiver With CDR-Less RX Front-End for On-Chip Links. - Jaeyoung Seo; Sooeun Lee; Myungguk Lee; Changjae Moon; Byungsub Kim (IEEE J. Solid State Circuits, 2023)

A Layout-to-Generator Conversion Framework With Graphical User Interface for Visual Programming of Analog Layout Generators. - Sungyu Jeong; Chanhyong Lee; Minsu Kim; Iksu Jang; Myungguk Lee; Junung Choi; Byungsub Kim (IEEE Access, 2024)

Compact Single-Ended Transceivers Demonstrating Flexible Generation of 1/N-Rate Receiver Front-Ends for Short-Reach Links. - Myungguk Lee; Jaeik Cho; Junung Choi; Won Joon Choi; Jiyun Lee; Iksu Jang; Changjae Moon; Gain Kim; Byungsub Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A Single-Ended Inverter-Based Addition-Only Feed-Forward Equalization Transmitter. - Changjae Moon; Jaeyoung Seo; Myungguk Lee; Iksu Jang; Byungsub Kim (IEEE J. Solid State Circuits, 2024)

3×16 Gb/s Compact Single-Ended PAM4 Transmitters With Inverter-Based Crosstalk Compensation for Memory Interfaces. - Changjae Moon; Iksu Jang; Sungmin Lim; Yaejoon Huh; Byungsub Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Fast Design Optimization of On-Chip Equalizing Links Using Particle Swarm Optimization. - Hyoseok Song; Kwangmin Kim; Gain Kim; Byungsub Kim (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A Self-Supervised Learning of a Foundation Model for Analog Layout Design Automation. - Sungyu Jeong; Won Joon Choi; Junung Choi; Anik Biswas; Byungsub Kim (CoRR, 2025)

An On-Chip Low-Cost Averaging Digital Sampling Scope for 80-GS/s Measurement of Wireline Pulse Responses. - Won Joon Choi; Myungguk Lee; Junung Choi; Jaeik Cho; Gain Kim; Byungsub Kim (IEEE Trans. Very Large Scale Integr. Syst., 2025)