Transistor Flaring in Deep Submicron-Design Considerations. - Vipul Singhal; C. B. Keshav; K. G. Surnanth; P. R. Suresh (ASP-DAC/VLSI Design, 2002)

Optimization of 1.8V I/O circuits for performance, reliability at the 100nm technology node. - Vinod Menezes; C. B. Keshav; Sushil Gupta; M. Roopashree; S. Krishnan; A. Amerasekera; G. Palau (VLSI Design, 2003)