Design issues of a rate 8/10 matched-spectral-null trellis code chip for partial response channels. - C. Bernard Shung; Paul H. Siegel; Hemant K. Thapar; Razmik Karabed (ICCD, 1990)

General in-place scheduling for the Viterbi algorithm. - Horng-Dar Lin; C. Bernard Shung (ICASSP, 1991)

Exact bounds for Viterbi detector path metric differences. - Paul H. Siegel; C. Bernard Shung; Thomas D. Howell; Hemant K. Thapar (ICASSP, 1991)

An integrated CAD system for algorithm-specific IC design. - C. Bernard Shung; Rajeev Jain; Ken Rimey; Edward Wang; Mani B. Srivastava; Brian C. Richards; Erik Lettang; Syed Khalid Azim; Lars E. Thon; Paul N. Hilfinger; Jan M. Rabaey; Robert W. Brodersen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

A 30-MHz trellis codec chip for partial-response channels. - C. Bernard Shung; Paul H. Siegel; Hemant K. Thapar; Razmik Karabed (IEEE J. Solid State Circuits, 1991)

Crossing distribution. - Deborah C. Wang; C. Bernard Shung (EURO-DAC, 1992)

A Multi-phase Shared Bus Structure for the Fast Fourier Transform. - Yu-Sheng Lin; Jiun-In Guo; C. Bernard Shung; Chein-Wei Jen (ISCAS, 1993)

Area-efficient architectures for the Viterbi algorithm. I. Theory. - C. Bernard Shung; Horng-Dar Lin; Robert Cypher; Paul H. Siegel; Hemant K. Thapar (IEEE Trans. Commun., 1993)

Area-efficient architectures for the Viterbi algorithm II. Applications. - C. Bernard Shung; Horng-Dar Lin; Robert Cypher; Paul H. Siegel; Hemant K. Thapar (IEEE Trans. Commun., 1993)

Generalized trace-back techniques for survivor memory management in the Viterbi algorithm. - Robert Cypher; C. Bernard Shung (J. VLSI Signal Process., 1993)

Fault-Tolerant Architectures for Shared Buffer Memory Switch. - Yeong-Fong Lin; C. Bernard Shung (ISCAS, 1994)

Queue Management for Shared Buffer and Shared Multi-Buffer ATM Switches. - Yu-Sheng Lin; C. Bernard Shung (INFOCOM, 1996)

Reactive Bandwidth Arbitration for Priority and Multicasting Control in ATM Switching. - Shu-Jen Fang; Yu-Sheng Lin; Shan-Chieh Yang; C. Bernard Shung (ICC (3), 1997)

Quasi-pushout cell discarding. - Yu-Sheng Lin; C. Bernard Shung (IEEE Commun. Lett., 1997)

Event-Driven Power Estimation of CMOS Circuits. - Wei-Chang Tsai; C. Bernard Shung (J. Circuits Syst. Comput., 1997)

A (208, 192;8) Reed-Solomon decoder for DVD application. - Hsie-Chia Chang; C. Bernard Shung (ICC, 1998)

A combined channel assignment mechanism for hierarchical cellular systems. - Kuen-Rong Lo; Chung-Ju Chang; Cooper Chang; C. Bernard Shung (Comput. Commun., 1998)

New serial architecture for the Berlekamp-Massey algorithm. - Hsie-Chia Chang; C. Bernard Shung (IEEE Trans. Commun., 1999)

Two systolic architectures for modular multiplication. - Wei-Chang Tsai; C. Bernard Shung; Sheng-Jyh Wang (IEEE Trans. Very Large Scale Integr. Syst., 2000)

A QoS-guaranteed fuzzy channel allocation controller for hierarchical cellular systems. - Kuen-Rong Lo; Chung-Ju Chang; Cooper Chang; C. Bernard Shung (IEEE Trans. Veh. Technol., 2000)

A Reed-Solomon product-code (RS-PC) decoder chip for DVD applications. - Hsie-Chia Chang; C. Bernard Shung; Chen-Yi Lee (IEEE J. Solid State Circuits, 2001)

A neural fuzzy resource manager for hierarchical cellular systems supporting multimedia services. - Kuen-Rong Lo; Chung-Ju Chang; C. Bernard Shung (IEEE Trans. Veh. Technol., 2003)

A 4-Gbps Uncompressed Wireless HD A/V Transceiver Chipset. - Jeffrey M. Gilbert; Chinh H. Doan; Sohrab Emami; C. Bernard Shung (IEEE Micro, 2008)