# C.-J. Richard Shi

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^{1}, C.-J. Richard Shi authored at least 104 papers between 1991 and 2018.Collaborative distances:

## Timeline

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## Bibliography

2018

A 10-bit 50-MS/s SAR ADC with 1 fJ/Conversion in 14 nm SOI FinFET CMOS.

Integration, 2018

OCEAN: An On-Chip Incremental-Learning Enhanced Artificial Neural Network Processor With Multiple Gated-Recurrent-Unit Accelerators.

IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

A 13.56MHz Wireless Power and Data Transfer Receiver Achieving 75.4% Effective-Power-Conversion Efficiency with 0.1% ASK Modulation Depth and 9.2mW Output Power.

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Exploring the programmability for deep learning processors: from architecture to tensorization.

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

A High-Efficiency Split-Merge Charge Pump for Solar Energy Harvesting.

IEEE Trans. on Circuits and Systems, 2017

OCEAN: An on-chip incremental-learning enhanced processor with gated recurrent neural network accelerators.

Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2016

Highly time-interleaved noise-shaped SAR ADC with reconfigurable order.

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A sub-nW mV-range programmable threshold comparator for near-zero-energy sensing.

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

Identifying DC bias conditions for maximum DC current in digitally-assisted analog design.

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2010

Symmetry-aware placement algorithm using transitive closure graph representation for analog integrated circuits.

I. J. Circuit Theory and Applications, 2010

Mixed-signal system-on-chip verification using a recursively-verifying-modeling (RVM) methodology.

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2008

Sliced Message Passing: High Throughput Overlapped Decoding of High-Rate Low-Density Parity-Check Codes.

IEEE Trans. on Circuits and Systems, 2008

Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Simulation of Closely Related Dynamic Nonlinear Systems With Application to Process-Voltage-Temperature Corner Analysis.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

A quantum-dot light-harvesting architecture using deterministic phase control.

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A 6-11GHz multi-phase VCO design with active inductors.

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Scalable Symbolic Model Order Reduction.

Proceedings of the 2008 IEEE International Behavioral Modeling and Simulation Workshop, 2008

Symmetry-aware placement with transitive closure graphs for analog layout design.

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

CASCADE: A Standard Supercell Design Methodology With Congestion-Driven Placement for Three-Dimensional Interconnect-Heavy Very Large-Scale Integrated Circuits.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

VHDL-AMS based modeling and simulation of mixed-technology microsystems: a tutorial.

Integration, 2007

Implementing a 2-Gbs 1024-bit 1/2-rate low-density parity-check code decoder in three-dimensional integrated circuits.

Proceedings of the 25th International Conference on Computer Design, 2007

Maximizing the throughput-area efficiency of fully-parallel low-density parity-check decoding with C-slow retiming and asynchronous deep pipelining.

Proceedings of the 25th International Conference on Computer Design, 2007

A Graph Reduction Approach to Symbolic Circuit Analysis.

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Code construction and FPGA implementation of a low-error-floor multi-rate low-density Parity-check code decoder.

IEEE Trans. on Circuits and Systems, 2006

Efficient DC fault simulation of nonlinear analog circuits: one-step relaxation and adaptive simulation continuation.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

On symbolic model order reduction.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

A Quasi-Newton Preconditioned Newton-Krylov Method for Robust and Efficient Time-Domain Simulation of Integrated Circuits With Strong Parasitic Couplings.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

SILCA: SPICE-accurate iterative linear-centric analysis for efficient time-domain Simulation of VLSI circuits with strong parasitic couplings.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Multilevel symmetry-constraint generation for retargeting large analog layouts.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

FROSTY: A program for fast extraction of high-level structural representation from circuit description for industrial CMOS circuits.

Integration, 2006

Improved automatic differentiation method for efficient model compiler.

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts.

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

A high-throughput low-power fully parallel 1024-bit 1/2-rate low density parity check code decoder in 3-dimensional integrated circuits.

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

A quasi-newton preconditioned Newton-Krylov method for robust and efficient time-domain simulation of integrated circuits with strong parasitic couplings.

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Model-order reduction by dominant subspace projection: error bound, subspace computation, and circuit applications.

IEEE Trans. on Circuits and Systems, 2005

Automatic Device Layout Generation for Analog Layout Retargeting.

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Bridging Circuits and Electromagnetics in a Curriculum Aimed at Microelectronic Analog and Microwave Simulation and Design.

Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005

Model-compiler based efficient statistical circuit analysis: an industry case study of a 4 GHz/6-bit ADC/DAC/DEMUX ASIC.

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Fast-yet-accurate PVT simulation by combined direct and iterative methods.

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Noise aware behavioral modeling of the E-Delta fractional-N frequency synthesizer.

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

VLSI implementation of a low-error-floor and capacity-approaching low-density parity-check code decoder with multi-rate capacity.

Proceedings of the Global Telecommunications Conference, 2005. GLOBECOM '05, St. Louis, Missouri, USA, 28 November, 2005

An Efficiently Preconditioned GMRES Method for Fast Parasitic-Sensitive Deep-Submicron VLSI Circuit Simulation.

Proceedings of the 2005 Design, 2005

Template-driven parasitic-aware optimization of analog integrated circuit layouts.

Proceedings of the 42nd Design Automation Conference, 2005

An FPGA implementation of low-density parity-check code decoder with multi-rate capability.

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Efficient approximation of symbolic expressions for analog behavioral modeling and analysis.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Circuit level modeling and simulation of mixed-technology systems.

Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Modeling and Simulation of Circuit-Electromagnetic Effects in Electronic Design Flow.

Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

A coupled iterative/direct method for efficient time-domain simulation of nonlinear circuits with power/ground networks.

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Hierarchical Multi-Dimensional Table Lookup for Model Compiler Based Circuit Simulation.

Proceedings of the 2004 Design, 2004

Correct-by-construction layout-centric retargeting of large analog designs.

Proceedings of the 41th Design Automation Conference, 2004

Parametric reduced order modeling for interconnect analysis.

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

CrtSmile: a CAD tool for CMOS RF transistor substrate modeling incorporating layout effects.

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Multiple specifications radio-frequency integrated circuit design with automatic template-driven layout retargeting.

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Hierarchical extraction and verification of symmetry constraints for analog layout automation.

2003

Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Efficient very large scale integration power/ground network sizing based on equivalent circuit modeling.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Balanced multi-level multi-way partitioning of analog integrated circuits for hierarchical symbolic analysis.

Integration, 2003

IPRAIL - intellectual property reuse-based analog IC layout automation.

Integration, 2003

Parametric Equivalent Circuit Extraction for VLSI Structures.

Proceedings of the IFIP VLSI-SoC 2003, 2003

Automatic analog layout retargeting for new processes and device sizes.

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Concurrent logic and interconnect delay estimation of MOS circuits by mixed algebraic and Boolean symbolic analysis.

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

FROSTY: A Fast Hierarchy Extractor for Industrial CMOS Circuits.

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

SILCA: Fast-Yet-Accurate Time-Domain Simulation of VLSI Circuits with Strong Parasitic Coupling Effects.

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Symbolic Analysis of Nonlinear Analog Circuits.

Proceedings of the 2003 Design, 2003

Symbolic analysis of analog circuits with hard nonlinearity.

Proceedings of the 40th Design Automation Conference, 2003

Efficient DDD-based term generation algorithm for analog circuit behavioral modeling.

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Coupled Electromagnetic-Circuit Simulation of Arbitrarily-Shaped Conducting Structures Using Triangular Meshes.

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

2001

Compact representation and efficient generation of s-expandedsymbolic network functions for computer-aided analog circuit design.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Lower Bound Based DDD Minimization for Efficient Symbolic Circuit Analysis.

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Distributed Event-Driven Simulation of VHDL-SPICE Mixed-Signal Circuits.

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Fast Power/Ground Network Optimization Based on Equivalent Circuit Modeling.

Proceedings of the 38th Design Automation Conference, 2001

2000

Hierarchical symbolic analysis of analog integrated circuits viadeterminant decision diagrams.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

Canonical symbolic analysis of large analog circuits withdeterminant decision diagrams.

IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

Parallel and Distributed VHDL Simulation.

Proceedings of the 2000 Design, 2000

Layout Compaction for Yield Optimization via Critical Area Minimization.

Proceedings of the 2000 Design, 2000

Multi-terminal determinant decision diagrams: a new approach to semi-symbolic analysis of analog integrated circuits.

Proceedings of the 37th Conference on Design Automation, 2000

Symbolic circuit-noise analysis and modeling with determinant decision diagrams.

Proceedings of ASP-DAC 2000, 2000

Analog-testability analysis by determinant-decision-diagrams based symbolic analysis.

Proceedings of ASP-DAC 2000, 2000

1999

Simulation and sensitivity of linear analog circuits under parameter variations by Robust interval analysis.

ACM Trans. Design Autom. Electr. Syst., 1999

A Characterization of Signed Hypergraphs and Its Applications to VLSI Via Minimization and Logic Synthesis.

Discrete Applied Mathematics, 1999

Distributed simulation of VLSI systems via lookahead-free self-adaptive optimistic and conservative synchronization.

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Interpretable Symbolic Small-Signal Characterization of Large Analog Circuits using Determinant Decision Diagrams.

Proceedings of the 1999 Design, 1999

Reliability-Constrained Area Optimization of VLSI Power/Ground Networks via Sequence of Linear Programmings.

Proceedings of the 36th Conference on Design Automation, 1999

Balanced Multi-Level Multi-Way Partitioning of Large Analog Circuits for Hierarchical Symbolic Analysis.

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

Symmetry Detection for Automatic Analog-Layout Recycling.

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998

Cluster-cover a theoretical framework for a class of VLSI-CAD optimization problems.

ACM Trans. Design Autom. Electr. Syst., 1998

Entity Overloading for Mixed-Signal Abstraction in VHDL.

J. Inf. Sci. Eng., 1998

Behavioral Level Noise Modeling and Jitter Simulation of Phase-Locked Loops with Faults Using VHDL-AMS.

J. Electronic Testing, 1998

Nonlinear Analog DC Fault Simulation by One-Step Relaxation.

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

Efficient DC Fault Simulation of Nonlinear Analog Circuits.

Proceedings of the 1998 Design, 1998

Automatic Test Generation for Linear Analog Circuits under Parameter Variations.

Proceedings of the ASP-DAC '98, 1998

Mixed-Signal Hardware Description Languages in the Era of System-on-Silicon: Challenges and Opportunities (Abstract of Embedded Tutorial).

Proceedings of the ASP-DAC '98, 1998

1997

Performance-Driven Layer Assignment by Integer Linear Programming and Path-Constrained Hypergraph Partitioning.

J. Heuristics, 1997

Behavioral level noise modeling and jitter simulation of phase-locked loops with faults using VHDL-AMS.

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Symbolic analysis of large analog circuits with determinant decision diagrams.

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Rapid Frequency-Domain Analog Fault Simulation Under Parameter Tolerances.

Proceedings of the 34st Conference on Design Automation, 1997

Solving constrained via minimization by compact linear programming.

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

Block-level fault isolation using partition theory and logic minimization techniques.

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996

Exact Dichotomy-based Constrained Encodi.

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Entity overloading for mixed-signal abstraction in VHDL.

Proceedings of the conference on European design automation, 1996

1995

A framework for the analysis and design of algorithms for a class of VLSI-CAD optimization problems.

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1992

A signed hypergraph model of constrained via minimization.

Proceedings of the Second Great Lakes Symposium on VLSI, 1992

Efficient constrained encoding for VLSI sequential logic synthesis.

Proceedings of the conference on European design automation, 1992

1991

Group delay as an estimate of delay in logic.

IEEE Trans. on CAD of Integrated Circuits and Systems, 1991