C. L. Liu

According to our database1, C. L. Liu
  • authored at least 135 papers between 1964 and 2012.
  • has a "Dijkstra number"2 of four.

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Bibliography

2012
I attended the nineteenth design automation conference.
Proceedings of the International Symposium on Physical Design, 2012

2005
The High Walls have Crumpled.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

2003
Noise-aware interconnect power optimization in domino logic synthesis.
IEEE Trans. VLSI Syst., 2003

Coupling delay optimization by temporal decorrelation using dual threshold voltage technique.
IEEE Trans. VLSI Syst., 2003

Compacting sequences with invariant transition frequencies.
ACM Trans. Design Autom. Electr. Syst., 2003

2002
Synthesis and Optimization of Combinational Interface Circuits.
VLSI Signal Processing, 2002

Logic transformation for low-power synthesis.
ACM Trans. Design Autom. Electr. Syst., 2002

Domino logic synthesis based on implication graph.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

A Complete Model for Glitch Analysis in Logic Circuits.
Journal of Circuits, Systems, and Computers, 2002

A technology mapping algorithm for CPLD architectures.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

2001
G-vector: A New Model for Glitch Analysis in Logic Circuits.
VLSI Signal Processing, 2001

Architecture driven circuit partitioning.
IEEE Trans. VLSI Syst., 2001

Optimization of the maximum delay of global interconnects duringlayer assignment.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Binary decision diagram with minimum expected path length.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique.
Proceedings of the 38th Design Automation Conference, 2001

2000
A postprocessing algorithm for crosstalk-driven wire perturbation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

Noise-aware power optimization for on-chip interconnect.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis.
Proceedings of the 37th Conference on Design Automation, 2000

1999
Partial Scan with Preselected Scan Signals.
IEEE Trans. Computers, 1999

The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

From Time Sharing to Real Time-Sharing of a Really Good Time in the Last 40 Years.
Proceedings of the 20th IEEE Real-Time Systems Symposium, 1999

An efficient data path synthesis algorithm for behavioral-level power optimization.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Optimal allocation of carry-save-adders in arithmetic optimization.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Implication graph based domino logic synthesis.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Logic Transformation for Low Power Synthesis.
Proceedings of the 1999 Design, 1999

Crosstalk Minimization Using Wire Perturbations.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Register Allocation - A Hierarchical Reduction Approach.
VLSI Signal Processing, 1998

Optimal clock period FPGA technology mapping for sequential circuits.
ACM Trans. Design Autom. Electr. Syst., 1998

Optimal clock period clustering for sequential circuits with retiming.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Low power logic synthesis under a general delay model.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Local transformation techniques for multi-level logiccircuits utilizing circuit symmetries for power reduction.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

A performance-driven layer assignment algorithm for multiple interconnect trees.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Power invariant vector sequence compaction.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Architecture driven circuit partitioning.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1997
Routing for symmetric FPGAs and FPICs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

Timing-driven placement for regular architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

Optimal Graph Constraint Reduction for Symbolic Layout Compaction.
Algorithmica, 1997

Optimal Clock Period Clustering for Sequential Circuits with Retiming.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Low power logic synthesis for XOR based circuits.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Low Power FPGA Design - A Re-engineering Approach.
Proceedings of the 34st Conference on Design Automation, 1997

1996
An integrated algorithm for incremental data path synthesis.
VLSI Signal Processing, 1996

Low power realization of finite state machines - a decomposition approach.
ACM Trans. Design Autom. Electr. Syst., 1996

Minimum crosstalk channel routing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

Area Minimization for Hierarchical Floorplans.
Algorithmica, 1996

An algorithm for synthesis of system-level interface circuits.
ICCAD, 1996

Technology Mapping of Sequential Circuits for LUT-Based FPGAs for Performance.
Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, 1996

A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs.
Proceedings of the Euro-Par '96 Parallel Processing, 1996

A Timing-Constrained Incremental Routing Algorithm for Symmetrical FPGAs.
Proceedings of the 1996 European Design and Test Conference, 1996

Timing Driven Placement Reconfiguration for Fault Tolerance and Yield Enhancement in FPGAs.
Proceedings of the 1996 European Design and Test Conference, 1996

Optimal Clock Period FPGA Technology Mapping for Sequential Circuits.
Proceedings of the 33st Conference on Design Automation, 1996

Desensitization for Power Reduction in Sequential Circuits.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Optimal Reconfiguration Algorithms for Real-Time Fault-Tolerant Processor Arrays.
IEEE Trans. Parallel Distrib. Syst., 1995

Area minimization for floorplans.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1995

A new approach to the multiport memory allocation problem in data path synthesis.
Integration, 1995

Minimum crosstalk switchbox routing.
Integration, 1995

Re-engineering of timing constrained placements for regular architectures.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs.
Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995

Partial Scan with Pre-selected Scan Signals.
Proceedings of the 32st Conference on Design Automation, 1995

1994
A scheduling algorithm for conditional resource sharing-a hierarchical reduction approach.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

Area minimization for hierarchical floorplans.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Compression-relaxation: a new approach to performance driven placement for regular architectures.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Minimum crosstalk switchbox routing.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

A delay driven FPGA placement algorithm.
Proceedings of the Proceedings EURO-DAC'94, 1994

Routing in a New 2-Dimensional FPGA/FPIC Routing Architecture.
Proceedings of the 31st Conference on Design Automation, 1994

1993
Modified Rate-Monotonic Algorithm for Scheduling Periodic Jobs with Deferred Deadlines.
IEEE Trans. Software Eng., 1993

Physical models and efficient algorithms for over-the-cell routing in standard cell design.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993

Routing for symmetric FPGAs and FPICs.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Minimum crosstalk channel routing.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Register allocation for data flow graphs with conditional branches and loops.
Proceedings of the European Design Automation Conference 1993, 1993

A performance driven hierarchical partitioning placement algorithm.
Proceedings of the European Design Automation Conference 1993, 1993

Optimal Graph Constraint Reduction for Symbolic Layout Compaction.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

Utilization of Multiport Memories in Data Path Synthesis.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
Fundamentals of Real-Time Scheduling (Extended Abstract).
Proceedings of the Real Time Computing, 1992

An Area Minimizer for Floorplans with L-Shaped Regions.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Area minimization for general floorplans.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

A Performance Driven Macro-Cell Placement Algorithm.
Proceedings of the 29th Design Automation Conference, 1992

1991
On the k-layer planar subset and topological via minimization problems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1991

Disjoint Covers in Replicated Heterogeneous Arrays.
SIAM J. Discrete Math., 1991

Minimum fault covering in reconfigurable arrays.
Integration, 1991

A Channel Router for Single Layer Customization Technology.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

A Scheduling Algorithm for Conditional Resource Sharing.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

A New Performance Driven Placement Algorithm.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

1990
Over-the-cell channel routing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1990

PLA logic minimization by simulated annealing.
Integration, 1990

Fault covers in reconfigurable PLAs.
Proceedings of the 20th International Symposium on Fault-Tolerant Computing, 1990

Solution of a module orientation and rotation problem.
Proceedings of the European Design Automation Conference, 1990

On the k-layer planar subset and via minimization problems.
Proceedings of the European Design Automation Conference, 1990

General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989
A new approach to the pin assignment problem.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1989

An enhanced bottom-up algorithm for floorplan design.
Integration, 1989

Generalized latin squares I.
Discrete Applied Mathematics, 1989

Floorplan Design of VLSI Circuits.
Algorithmica, 1989

Constrained floorplan design for flexible blocks.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

Solutions to the Module Orientation and Rotation Problems by Neural Computation Networks.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988
A new approach to three- or four-layer channel routing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1988

A new formulation of yield enhancement problems for reconfigurable chips.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

Over-the-cell channel routing.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

Minimum fault coverage in reconfigurable arrays.
Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988

A New Approach to the Pin Assignment Problem.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987
Algorithms for permutation channel routing.
Integration, 1987

Array Optimization for VLSI Synthesis.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, June 28, 1987

1986
An Algorithmic Proof of a Generalization of the Birkhoff-Von Neumann Theorem.
J. Algorithms, 1986

Compacted channel routing with via placement restrictions.
Integration, 1986

A new algorithm for floorplan design.
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, NV, June, 1986., 1986

1985
Permutation Representation of k-Ary Trees.
Theor. Comput. Sci., 1985

1984
Bipartite Folding and Partitioning of a PLA.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1984

A Personnel Assignment Problem.
J. Algorithms, 1984

1983
(g 0, g 1, ... g k)-Trees and Unary OL Systems.
Theor. Comput. Sci., 1983

On a Periodic Maintenance Problem.
Oper. Res. Lett., 1983

1982
Scheduling with Slack Time.
Acta Inf., 1982

Optimal bipartite folding of PLA.
Proceedings of the 19th Design Automation Conference, 1982

1980
Generation of trees.
Proceedings of the Proc. 5eme Colleque de Lille sur les Arbres en Algebre et en Programmation, 1980

1978
On a Real-Time Scheduling Problem.
Operations Research, 1978

A generalization of Ramsey theory for graphs.
Discrete Mathematics, 1978

Performance Analysis of Multiprocessor Systems Containing Functionally Dedicated Processors.
Acta Inf., 1978

1976
Deterministic Job Scheduling in Computing Systems.
Proceedings of the Modelling and Performance Evaluation of Computer Systems, 1976

1975
Sperner's theorem on maximal-sized antichains and its generalization.
Discrete Mathematics, 1975

1974
On a Class of Scheduling Algorithms for Multiprocessors Computing Systems.
Proceedings of the Parallel Processing, 1974

Bounds on Scheduling Algorithms for Heterogeneous Comnputing Systems.
IFIP Congress, 1974

1973
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment.
J. ACM, 1973

A construction scheme for linear and non-linear codes.
Discrete Mathematics, 1973

A drum scheduling algorithm.
Proceedings of the 1. Fachtagung über Automatentheorie und Formale Sprachen, 1973

Analysis of sorting algorithms.
Proceedings of the American Federation of Information Processing Societies: 1973 National Computer Conference, 1973

1972
Complementary sets of sequences.
IEEE Trans. Information Theory, 1972

Analysis and Synthesis of Sorting Algorithms.
SIAM J. Comput., 1972

Optimal Scheduling on Multi-Processor Computing Systems
Proceedings of the 13th Annual Symposium on Switching and Automata Theory, 1972

1971
Analysis of Sorting Algorithms
Proceedings of the 12th Annual Symposium on Switching and Automata Theory, 1971

1969
A Note on Definite Stochastic Sequential Machines
Information and Control, April, 1969

Lattice Functions, Pair Algebras, and Finite-State Machines.
J. ACM, 1969

1967
The design and implementation of a table driven compiler system.
Proceedings of the American Federation of Information Processing Societies: Proceedings of the AFIPS '67 Spring Joint Computer Conference, 1967

1966
Some algebraic properties of multi-threshold functions.
IEEE Trans. Electronic Computers, 1966

Pair Algebra and Its Application
Proceedings of the 7th Annual Symposium on Switching and Automata Theory, 1966

1964
kth-Order Finite Automaton.
IEEE Trans. Electronic Computers, 1964

Sequential-machine realization using feedback shift registers
Proceedings of the 5th Annual Symposium on Switching Circuit Theory and Logical Design, 1964


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