Sequential-machine realization using feedback shift registers - C. L. Liu 001 (SWCT, 1964)

kth-Order Finite Automaton. - C. L. Liu 001 (IEEE Trans. Electron. Comput., 1964)

Pair Algebra and Its Application - C. L. Liu 001 (SWAT, 1966)

Some algebraic properties of multi-threshold functions. - C. L. Liu 001 (IEEE Trans. Electron. Comput., 1966)

The design and implementation of a table driven compiler system. - C. L. Liu 001; G. D. Chang; R. E. Marks (AFIPS Spring Joint Computing Conference, 1967)

Lattice Functions, Pair Algebras, and Finite-State Machines. - C. L. Liu 001 (J. ACM, 1969)

A Note on Definite Stochastic Sequential Machines - C. L. Liu 001 (Inf. Control., 1969)

Optimal Scheduling on Multi-Processor Computing Systems - C. L. Liu 001 (SWAT, 1972)

Analysis and Synthesis of Sorting Algorithms. - C. L. Liu 001 (SIAM J. Comput., 1972)

Complementary sets of sequences. - Chin-Chong Tseng; C. L. Liu 001 (IEEE Trans. Inf. Theory, 1972)

Analysis of sorting algorithms. - C. L. Liu 001 (AFIPS National Computer Conference, 1973)

A drum scheduling algorithm. - C. K. Wong; C. L. Liu 001; J. Apter (Automatentheorie und Formale Sprachen, 1973)

A construction scheme for linear and non-linear codes. - C. L. Liu 001; B. G. Ong; Gregory R. Ruth (Discret. Math., 1973)

Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment. - C. L. Liu 001; James W. Layland (J. ACM, 1973)

Bounds on Scheduling Algorithms for Heterogeneous Comnputing Systems. - Jane W.-S. Liu; C. L. Liu 001 (IFIP Congress, 1974)

On a Class of Scheduling Algorithms for Multiprocessors Computing Systems. - N. F. Chen; C. L. Liu 001 (Sagamore Computer Conference, 1974)

Sperner's theorem on maximal-sized antichains and its generalization. - C. L. Liu 001 (Discret. Math., 1975)

Deterministic Job Scheduling in Computing Systems. - C. L. Liu 001 (Performance, 1976)

Performance Analysis of Multiprocessor Systems Containing Functionally Dedicated Processors. - Jane W.-S. Liu; C. L. Liu 001 (Acta Informatica, 1978)

A generalization of Ramsey theory for graphs. - K. M. Chung; C. L. Liu 001 (Discret. Math., 1978)

On a Real-Time Scheduling Problem. - Sudarshan K. Dhall; C. L. Liu 001 (Oper. Res., 1978)

Generation of trees. - C. L. Liu 001 (CLAAP, 1980)

Optimal bipartite folding of PLA. - Jack R. Egan; C. L. Liu 001 (DAC, 1982)

Scheduling with Slack Time. - C. L. Liu 001; Jane W.-S. Liu; Arthur L. Liestman (Acta Informatica, 1982)

A new channel routing problem. - Hon Wai Leong; C. L. Liu 001 (DAC, 1983)

On a Periodic Maintenance Problem. - W.-D. Wei; C. L. Liu 001 (Oper. Res. Lett., 1983)

SS/TDMA Time Slot Assignment with Restricted Switching Modes. - James L. Lewandowski; Jane W.-S. Liu; C. L. Liu 001 (IEEE Trans. Commun., 1983)

(g 0, g 1, ... g k)-Trees and Unary OL Systems. - D. T. Lee; C. L. Liu 001; C. K. Wong (Theor. Comput. Sci., 1983)

A branch and bound algorithm for optimal pla folding. - James L. Lewandowski; C. L. Liu 001 (DAC, 1984)

A Personnel Assignment Problem. - Prakash V. Ramanan; Jitender S. Deogun; C. L. Liu 001 (J. Algorithms, 1984)

Bipartite Folding and Partitioning of a PLA. - Jack R. Egan; C. L. Liu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984)

Permutation Representation of k-Ary Trees. - Prakash V. Ramanan; C. L. Liu 001 (Theor. Comput. Sci., 1985)

A new algorithm for floorplan design. - D. F. Wong 001; C. L. Liu 001 (DAC, 1986)

Compacted channel routing with via placement restrictions. - D. F. Wong 001; C. L. Liu 001 (Integr., 1986)

An Algorithmic Proof of a Generalization of the Birkhoff-Von Neumann Theorem. - James L. Lewandowski; C. L. Liu 001; Jane W.-S. Liu (J. Algorithms, 1986)

Array Optimization for VLSI Synthesis. - D. F. Wong 001; C. L. Liu 001 (DAC, 1987)

Algorithms for permutation channel routing. - H. W. Leong; C. L. Liu 001 (Integr., 1987)

A New Approach to the Pin Assignment Problem. - Xianji Yao; Masaaki Yamada; C. L. Liu 001 (DAC, 1988)

Minimum fault coverage in reconfigurable arrays. - Nany Hasan; C. L. Liu 001 (FTCS, 1988)

Over-the-cell channel routing. - Jingsheng Cong; C. L. Liu 001 (ICCAD, 1988)

A new formulation of yield enhancement problems for reconfigurable chips. - Nany Hasan; Jason Cong; C. L. Liu 001 (ICCAD, 1988)

A new approach to three- or four-layer channel routing. - Jason Cong; Martin D. F. Wong; C. L. Liu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

Solutions to the Module Orientation and Rotation Problems by Neural Computation Networks. - Ran Libeskind-Hadas; C. L. Liu 001 (DAC, 1989)

Constrained floorplan design for flexible blocks. - Sai-keung Dong; Jason Cong; C. L. Liu 001 (ICCAD, 1989)

Floorplan Design of VLSI Circuits. - D. F. Wong 001; C. L. Liu 001 (Algorithmica, 1989)

Generalized latin squares I. - Xiaojun Shen; Y. Z. Cai; C. L. Liu 001; Clyde P. Kruskal (Discret. Appl. Math., 1989)

An enhanced bottom-up algorithm for floorplan design. - Thomas R. Mueller; D. F. Wong 001; C. L. Liu 001 (Integr., 1989)

A new approach to the pin assignment problem. - Xianjin Yao; Masaaki Yamada; C. L. Liu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design. - Jason Cong; Bryan Preas; C. L. Liu 001 (DAC, 1990)

On the k-layer planar subset and via minimization problems. - Jason Cong; C. L. Liu 001 (EURO-DAC, 1990)

Solution of a module orientation and rotation problem. - Xianjin Yao; C. L. Liu 001 (EURO-DAC, 1990)

Fault covers in reconfigurable PLAs. - Nany Hasan; C. L. Liu 001 (FTCS, 1990)

PLA logic minimization by simulated annealing. - Xianjin Yao; C. L. Liu 001 (Integr., 1990)

Over-the-cell channel routing. - Jason Cong; C. L. Liu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

A New Performance Driven Placement Algorithm. - Tong Gao; Pravo M. Vaidya; C. L. Liu 001 (ICCAD, 1991)

A Scheduling Algorithm for Conditional Resource Sharing. - Taewhan Kim 001; Jane W.-S. Liu; C. L. Liu 001 (ICCAD, 1991)

A Channel Router for Single Layer Customization Technology. - Yachyang Sun; Sai-keung Dong; Shinji Sato; C. L. Liu 001 (ICCAD, 1991)

Minimum fault covering in reconfigurable arrays. - Nany Hasan; C. L. Liu 001 (Integr., 1991)

Disjoint Covers in Replicated Heterogeneous Arrays. - Philip K. McKinley; Nany Hasan; Ran Libeskind-Hadas; C. L. Liu 001 (SIAM J. Discret. Math., 1991)

On the k-layer planar subset and topological via minimization problems. - Jason Cong; C. L. Liu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

A Performance Driven Macro-Cell Placement Algorithm. - Tong Gao; Pravin M. Vaidya; C. L. Liu 001 (DAC, 1992)

Area minimization for general floorplans. - Peichen Pan; C. L. Liu 001 (ICCAD, 1992)

An Area Minimizer for Floorplans with L-Shaped Regions. - Yachyang Sun; C. L. Liu 001 (ICCD, 1992)

Fundamentals of Real-Time Scheduling (Extended Abstract). - C. L. Liu 001 (NATO ASI RTC, 1992)

Utilization of Multiport Memories in Data Path Synthesis. - Taewhan Kim 001; C. L. Liu 001 (DAC, 1993)

A performance driven hierarchical partitioning placement algorithm. - Tong Gao; Chung Laung (Dave) Liu; Kuang-Chien Chen (EURO-DAC, 1993)

Register allocation for data flow graphs with conditional branches and loops. - Chaeryung Park; Taewhan Kim 001; C. L. Liu 001 (EURO-DAC, 1993)

Physical models and efficient algorithms for over-the-cell routing in standard cell design. - Jason Cong; Bryan Preas; C. L. Liu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Modified Rate-Monotonic Algorithm for Scheduling Periodic Jobs with Deferred Deadlines. - Wei-Kuan Shih; Jane W.-S. Liu; C. L. Liu 001 (IEEE Trans. Software Eng., 1993)

Routing in a New 2-Dimensional FPGA/FPIC Routing Architecture. - Yachyang Sun; C. L. Liu 001 (DAC, 1994)

A delay driven FPGA placement algorithm. - Srilata Raman; C. L. Liu 001; Larry G. Jones (EURO-DAC, 1994)

Compression-relaxation: a new approach to performance driven placement for regular architectures. - Anmol Mathur; C. L. Liu 001 (ICCAD, 1994)

A scheduling algorithm for conditional resource sharing-a hierarchical reduction approach. - Taewhan Kim 001; Noritake Yonezawa; Jane W.-S. Liu; C. L. Liu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Partial Scan with Pre-selected Scan Signals. - Peichen Pan; C. L. Liu 001 (DAC, 1995)

Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs. - Anmol Mathur; Kuang-Chien Chen; C. L. Liu 001 (FPGA, 1995)

Re-engineering of timing constrained placements for regular architectures. - Anmol Mathur; Kuang-Chien Chen; C. L. Liu 001 (ICCAD, 1995)

Minimum crosstalk switchbox routing. - Tong Gao; C. L. Liu 001 (Integr., 1995)

A new approach to the multiport memory allocation problem in data path synthesis. - Taewhan Kim 001; C. L. Liu 001 (Integr., 1995)

Area minimization for floorplans. - Peichen Pan; C. L. Liu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Optimal Reconfiguration Algorithms for Real-Time Fault-Tolerant Processor Arrays. - Ran Libeskind-Hadas; Nimish Shrivastava; Rami G. Melhem; C. L. Liu 001 (IEEE Trans. Parallel Distributed Syst., 1995)

Desensitization for Power Reduction in Sequential Circuits. - Xiangfeng Chen; Peichen Pan; C. L. Liu 001 (DAC, 1996)

Timing Driven Placement Reconfiguration for Fault Tolerance and Yield Enhancement in FPGAs. - Anmol Mathur; C. L. Liu 001 (ED&TC, 1996)

A Timing-Constrained Incremental Routing Algorithm for Symmetrical FPGAs. - Srilata Raman; C. L. Liu 001; Larry G. Jones (ED&TC, 1996)

A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs. - Vamsi Boppana; Prashant Saxena; Prithviraj Banerjee; W. Kent Fuchs; C. L. Liu 001 (Euro-Par, Vol. I, 1996)

Technology Mapping of Sequential Circuits for LUT-Based FPGAs for Performance. - Peichen Pan; C. L. Liu 001 (FPGA, 1996)

An algorithm for synthesis of system-level interface circuits. - Ki-Seok Chung; Rajesh K. Gupta 001; C. L. Liu 001 (ICCAD, 1996)

Area Minimization for Hierarchical Floorplans. - Peichen Pan; Weiping Shi; C. L. Liu 001 (Algorithmica, 1996)

Minimum crosstalk channel routing. - Tong Gao; C. L. Liu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Low power realization of finite state machines - a decomposition approach. - Sue-Hong Chow; Yi-Cheng Ho; TingTing Hwang; C. L. Liu 001 (ACM Trans. Design Autom. Electr. Syst., 1996)

Timing-Constrained FPGA Placement: A Force-Directed Formulation and Its Performance Evaluation. - Srilata Raman; C. L. Liu 001; Larry G. Jones (VLSI Design, 1996)

An integrated algorithm for incremental data path synthesis. - Taewhan Kim 001; C. L. Liu 001 (J. VLSI Signal Process., 1996)

Low Power FPGA Design - A Re-engineering Approach. - Chau-Shen Chen; TingTing Hwang; C. L. Liu 001 (DAC, 1997)

Low power logic synthesis for XOR based circuits. - Unni Narayanan; C. L. Liu 001 (ICCAD, 1997)

Optimal Graph Constraint Reduction for Symbolic Layout Compaction. - Peichen Pan; Sai-keung Dong; C. L. Liu 001 (Algorithmica, 1997)

Timing-driven placement for regular architectures. - Anmol Mathur; C. L. Liu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Routing for symmetric FPGAs and FPICs. - Yachyang Sun; Ting-Chi Wang; Chak-Kuen Wong; C. L. Liu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Power invariant vector sequence compaction. - Ali Pinar; C. L. Liu 001 (ICCAD, 1998)

A performance-driven layer assignment algorithm for multiple interconnect trees. - Prashant Saxena; C. L. Liu 001 (ICCAD, 1998)

Local transformation techniques for multi-level logiccircuits utilizing circuit symmetries for power reduction. - Ki-Seok Chung; C. L. Liu 001 (ISLPED, 1998)

Low power logic synthesis under a general delay model. - Unni Narayanan; Peichen Pan; C. L. Liu 001 (ISLPED, 1998)

Optimal clock period clustering for sequential circuits with retiming. - Peichen Pan; Arvind K. Karandikar; C. L. Liu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Optimal clock period FPGA technology mapping for sequential circuits. - Peichen Pan; C. L. Liu 001 (ACM Trans. Design Autom. Electr. Syst., 1998)

Register Allocation - A Hierarchical Reduction Approach. - Chaeryung Park; Taewhan Kim 001; C. L. Liu 001 (J. VLSI Signal Process., 1998)

Crosstalk Minimization Using Wire Perturbations. - Prashant Saxena; C. L. Liu 001 (DAC, 1999)

Logic Transformation for Low Power Synthesis. - Ki-Wook Kim; Sung-Mo Kang; TingTing Hwang; C. L. Liu 001 (DATE, 1999)

Implication graph based domino logic synthesis. - Ki-Wook Kim; C. L. Liu 001; Sung-Mo Kang (ICCAD, 1999)

Optimal allocation of carry-save-adders in arithmetic optimization. - Junhyung Um; Taewhan Kim 001; C. L. Liu 001 (ICCAD, 1999)

An efficient data path synthesis algorithm for behavioral-level power optimization. - Chaeryung Park; Taewhan Park; C. L. Liu 001 (ISCAS (1), 1999)

From Time Sharing to Real Time-Sharing of a Really Good Time in the Last 40 Years. - C. L. Liu 001 (RTSS, 1999)

The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches. - Prashant Saxena; Peichen Pan; C. L. Liu 001 (VLSI Design, 1999)

Partial Scan with Preselected Scan Signals. - Peichen Pan; C. L. Liu 001 (IEEE Trans. Computers, 1999)

A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis. - Junhyung Um; Taewhan Kim 001; C. L. Liu 001 (DAC, 2000)

Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. - Ki-Wook Kim; Kwang-Hyun Baek; Naresh R. Shanbhag; C. L. Liu 001; Sung-Mo Kang (ICCAD, 2000)

Noise-aware power optimization for on-chip interconnect. - Ki-Wook Kim; Seong-Ook Jung; Unni Narayanan; C. L. Liu 001; Sung-Mo Kang (ISLPED, 2000)

A postprocessing algorithm for crosstalk-driven wire perturbation. - Prashant Saxena; C. L. Liu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

An Integrated Approach to Data Path Synthesis for Behavioral-level Power Optimization. - Chaeryung Park; Taewhan Kim 001; C. L. Liu 001 (VLSI Design, 2000)

Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. - Ki-Wook Kim; Seong-Ook Jung; Prashant Saxena; C. L. Liu 001; Sung-Mo Kang (DAC, 2001)

Binary decision diagram with minimum expected path length. - Yi-Yu Liu; Kuo-Hua Wang; TingTing Hwang; C. L. Liu 001 (DATE, 2001)

Optimization of the maximum delay of global interconnects duringlayer assignment. - Prashant Saxena; C. L. Liu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Architecture driven circuit partitioning. - Chau-Shen Chen; TingTing Hwang; C. L. Liu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2001)

G-vector: A New Model for Glitch Analysis in Logic Circuits. - Ki-Seok Chung; Taewhan Kim 001; C. L. Liu 001 (J. VLSI Signal Process., 2001)

Modularized low temperature LNO/PZT/LNO ferroelectric capacitor-over-interconnect (COI) FeRAM for advanced SOC (ASOC) application. - S. L. Lung; Dennis Lin; S. S. Chen; Gary Weng; C. L. Liu 001; S. C. Lai; C. W. Tsai; T. B. Wu; Rich Liu (CICC, 2002)

A technology mapping algorithm for CPLD architectures. - Shih-Liang Chen; TingTing Hwang; C. L. Liu 001 (FPT, 2002)

A Complete Model for Glitch Analysis in Logic Circuits. - Ki-Seok Chung; Taewhan Kim 001; C. L. Liu 001 (J. Circuits Syst. Comput., 2002)

Domino logic synthesis based on implication graph. - Ki-Wook Kim; Taewhan Kim 001; C. L. Liu 001; Sung-Mo Kang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Logic transformation for low-power synthesis. - Ki-Wook Kim; Taewhan Kim 001; TingTing Hwang; Sung-Mo Kang; C. L. Liu 001 (ACM Trans. Design Autom. Electr. Syst., 2002)

Synthesis and Optimization of Combinational Interface Circuits. - Ki-Seok Chung; Rajesh K. Gupta 001; Taewhan Kim 001; C. L. Liu 001 (J. VLSI Signal Process., 2002)

Compacting sequences with invariant transition frequencies. - Ali Pinar; C. L. Liu 001 (ACM Trans. Design Autom. Electr. Syst., 2003)

Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. - Ki-Wook Kim; Seong-Ook Jung; Taewhan Kim 001; Prashant Saxena; C. L. Liu 001; S.-M. S. Kang (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Noise-aware interconnect power optimization in domino logic synthesis. - Ki-Wook Kim; Seong-Ook Jung; Unni Narayanan; C. L. Liu 001; Sung-Mo Kang (IEEE Trans. Very Large Scale Integr. Syst., 2003)

The High Walls have Crumpled. - C. L. Liu 001 (VLSI Design, 2005)

I attended the nineteenth design automation conference. - C. L. Liu 001 (ISPD, 2012)