Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below. - Claire Fenouillet-Béranger; P. Perreau; S. Denorme; L. Tosti; François Andrieu; Olivier Weber; S. Barnola; C. Arvet; Y. Campidelli; Sébastien Haendler; R. Beneyton; C. Perrot; et al. (ESSCIRC, 2009)

Charging control on high energy implanters: A process requirement demonstrated by plasma damage monitoring. - C. Cantin; C. Laviron; G. Gove (Microelectron. Reliab., 2009)

Wafer level encapsulated materials evaluation for chip on wafer (CoW) approach in 2.5D Si interposer integration. - Sylvain Joblot; Alexis Farcy; Nicolas Hotellier; Amadine Jouve; François de Crecy; Arnaud Garnier; M. Argoud; C. Ferrandon; J.-P. Colonna; R. Franiatte; C. Laviron; Séverine Cheramy (3DIC, 2013)

Which interconnects for which 3D applications? Status and perspectives. - Yann Lamy; Jean-Philippe Colonna; G. Simon; Patrick Leduc; Séverine Cheramy; C. Laviron (3DIC, 2013)

Thermal correlation between measurements and FEM simulations in 3D ICs. - Papa Momar Souare; François de Crecy; Vincent Fiori; M. Haykel Ben Jamaa; Alexis Farcy; Sébastien Gallois-Garreignot; Andras Borbely; Jean-Philippe Colonna; Perceval Coudrain; B. Giraud; C. Laviron; Séverine Cheramy; et al. (3DIC, 2013)