Qualitative assessment of epitaxial graphene FETs on SiC substrates via pulsed measurements and temperature variation. - C. Mukherjee 001; Sébastien Fregonese; Thomas Zimmer; Cristell Maneux; Henri Happy; David Mele (ESSDERC, 2014)

A new physics-based compact model for Bilayer Graphene Field-Effect Transistors. - Jorgue Daniel Aguirre Morales; Sébastien Fregonese; C. Mukherjee 001; Cristell Maneux; Thomas Zimmer (ESSDERC, 2015)

Characterization and modeling of low-frequency noise in CVD-grown graphene FETs. - C. Mukherjee 001; Jorgue Daniel Aguirre Morales; Sébastien Fregonese; Thomas Zimmer; Cristell Maneux; Henri Happy; Wei Wei (ESSDERC, 2015)

Physics-based electrical compact model for monolayer Graphene FETs. - Jorgue Daniel Aguirre Morales; Sébastien Fregonese; C. Mukherjee 001; Cristell Maneux; Thomas Zimmer; Wei Wei; Henri Happy (ESSDERC, 2016)

Comprehensive study of random telegraph noise in base and collector of advanced SiGe HBT: Bias, geometry and trap locations. - C. Mukherjee 001; Thomas Jacquet; Thomas Zimmer; Cristell Maneux; Anjan Chakravorty; Josef Boeck; Klaus Aufinger (ESSDERC, 2016)

1/f Noise in 3D vertical gate-all-around junction-less silicon nanowire transistors. - Chhandak Mukherjee; Cristell Maneux; Julien Pezard; Guilhem Larrieu (ESSDERC, 2017)

Random telegraph noise in SiGe HBTs: Reliability analysis close to SOA limit. - C. Mukherjee 001; Thomas Jacquet; Anjan Chakravorty; Thomas Zimmer; Josef Boeck; Klaus Aufinger; Cristell Maneux (Microelectron. Reliab., 2017)

First Uni-Traveling Carrier Photodiode Compact Model Enabling Future Terahertz Communication System Design. - Chhandak Mukherjee; Patrick Mounaix; Cristell Maneux; Michele Natrella; James Seddon; Chris Graham; Cyril C. Renaud (ESSDERC, 2019)

3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model. - Arnaud Poittevin; Chhandak Mukherjee; Ian O'Connor; Cristell Maneux; Guilhem Larrieu; Marina Deng; Sébastien Le Beux; François Marc; Aurélie Lecestre; Cédric Marchand 002; Abhishek Kumar (VLSI-SoC (Selected Papers), 2020)

3D logic cells design and results based on Vertical NWFET technology including tied compact model. - C. Mukherjee 001; Marina Deng; François Marc; Cristell Maneux; Arnaud Poittevin; Ian O'Connor; Sébastien Le Beux; Abhishek Kumar; Aurélie Lecestre; Guilhem Larrieu (CoRR, 2020)

0.4-μm InP/InGaAs DHBT with a 380-GHz ${f_{T}}$, > 600-GHz $f_{ max}$ and BVCE0 > 4.5 V. - Nil Davy; Virginie Nodjiadjim; Muriel Riet; Colin Mismer; Marina Deng; Chhandak Mukherjee; Jérémie Renaudier; Cristell Maneux (BCICTS, 2021)

InP DHBT Characterization up to 500 GHz and Compact Model Validation Towards THz Circuit Design. - Marina Deng; Chhandak Mukherjee; Nil Davy; Virginie Nodjiadjim; Muriel Riet; Colin Mismer; Jérémie Renaudier; Magali De Matos; Cristell Maneux (BCICTS, 2021)

Electro-Thermal Limitations and Device Degradation of SiGe HBTs with Emphasis on Circuit Performance. - Sébastien Fregonese; Chhandak Mukherjee; Holger Rücker; Pascal Chevalier 002; Gerhard Fischer; Didier Céli; Marina Deng; Marine Couret; François Marc; Cristell Maneux; Thomas Zimmer (BCICTS, 2021)

Impact of Hot Carrier Degradation on the Performances of Current Mirrors based on a 55 nm BiCMOS Integrated Circuit Technology. - C. Mukherjee 001; Marine Couret; Cristell Maneux; Didier Céli (ESSDERC, 2021)

InP DHBT test structure optimization towards 110 GHz characterization. - Nil Davy; Marina Deng; Virginie Nodjiadjim; Chhandak Mukherjee; Muriel Riet; Colin Mismer; Jérémie Renaudier; Cristell Maneux (ESSDERC, 2022)

A Logic Cell Design and routing Methodology Specific to VNWFET. - Arnaud Poittevin; Ian O'Connor; Cédric Marchand 002; Alberto Bosio; Cristell Maneux; Chhandak Mukherjee; Guilhem Larrieu; Abhishek Kumar (NEWCAS, 2022)

Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors. - Lucas Réveil; Chhandak Mukherjee; Cristell Maneux; Marina Deng; François Marc; Abhishek Kumar; Aurélie Lecestre; Guilhem Larrieu; Arnaud Poittevin; Ian O'Connor; Oskar Baumgartner; David Pirker (VLSI-SoC, 2022)

Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design. - Yifan Wang; Chhandak Mukherjee; Houssem Rezgui; Marina Deng; Cristell Maneux; Sara Mannaa; Ian O'Connor; Jonas Müller; Sylvain Pelloquin; Guilhem Larrieu (ESSDERC, 2023)

SPICE Modeling in Verilog-A for Photo-Response in UTC-Photodiodes Targeting Beyond-5G Circuit Design. - C. Mukherjee 001; Djeber Guendouz; Marina Deng; H. Bertin; Antoine Bobin; Nicolas Vaissiere; Christophe Caillaud; Akshay M. Arabhavi; Rimjhim Chaudhary; Olivier Ostinelli; Colombo R. Bolognesi; Patrick Mounaix; et al. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

InP DHBT Analytical Modeling: Toward THz Transistors. - Nil Davy; Virginie Nodjiadjim; Muriel Riet; Colin Mismer; Marina Deng; Chhandak Mukherjee; Bertrand Ardouin; Cristell Maneux (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

FVLLMONTI: The 3D Neural Network Compute Cube $(N^{2}C^{2})$ Concept for Efficient Transformer Architectures Towards Speech-to-Speech Translation. - Ian O'Connor; Sara Mannaa; Alberto Bosio; Bastien Deveautour; Damien Deleruyelle; Tetiana Obukhova; Cédric Marchand 002; Jens Trommer; Çigdem Çakirlar; Bruno Neckel Wesling; Thomas Mikolajick; Oskar Baumgartner; et al. (DATE, 2024)

Multi-Partner Project: Smart Sensor Analog Front-Ends Powered by Emerging Reconfigurable Devices (SENSOTERIC). - Giulio Galderisi; Andreas Kramer; Andreas Fuchsberger; Jose Maria Gonzalez-Medina; Yuxuan He; Lee-Chi Hung; Marrit Jen Hong Li; Julian Kulenkampff; Maximilian Reuter; Lukas Wind; Masiar Sistani; Thomas Mikolajick; et al. (DATE, 2025)