Design of FFT processor using low power Vedic multiplier for wireless communication. - C. Padma; P. Jagadamba; P. Ramana Reddy (Comput. Electr. Eng., 2021)

Design of a 64-bit SQRT-CSLA with Reduced Area and High-Speed Applications in Low Power VLSI Circuits. - CH. Pallavi; C. Padma; R. Kiran Kumar; T. Suguna; C. Nalini (CoRR, 2024)