A Comprehensive Solution for True Hierarchical Timing and Crosstalk Delay Signoff. - K. A. Rajagopal; R. Sivakumar; N. V. Arvind; C. Sreeram; Vish Visvanathan; Shailendra Dhuri; Roopesh Chander; Patrick Fortner; Subra Sripada; Qiuyang Wu (VLSI Design, 2006)