The design of a high-performance scalable architecture for image processing applications. - C. Thomas Gray; Wentai Liu; Thomas A. Hughes; Ralph K. Cavin III (ASAP, 1990)

P3A: a partitionable parallel/pipeline architecture for real-time image processing. - C. Thomas Gray; Wentai Liu; Thomas A. Hughes; Ralph K. Cavin III; Su-Shing Chen (ICPR (2), 1990)

Theoretical and Practical Issues in CMOS Wave Pipelining. - C. Thomas Gray; Thomas A. Hughes; Sanjay Arora; Wentai Liu; Ralph K. Cavin III (VLSI, 1991)

Circuit delay calculation considering data dependent delays. - C. Thomas Gray; Wentai Liu; Ralph K. Cavin III; Hong-Yean Hsieh (Integr., 1994)

Timing constraints for wave-pipelined systems. - C. Thomas Gray; Wentai Liu; Ralph K. Cavin III (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

A sampling technique and its CMOS implementation with 1 Gb/s bandwidth and 25 ps resolution. - C. Thomas Gray; Wentai Liu; Wilhelmus A. M. Van Noije; Thomas A. Hughes; Ralph K. Cavin III (IEEE J. Solid State Circuits, 1994)

A 250-MHz wave pipelined adder in 2-μm CMOS. - Wentai Liu; C. Thomas Gray; David Fan; William J. Farlow; Thomas A. Hughes; Ralph K. Cavin III (IEEE J. Solid State Circuits, 1994)

Concurrent timing optimization of latch-based digital systems. - Hong-Yean Hsieh; Wentai Liu; Ralph K. Cavin III; C. Thomas Gray (ICCD, 1995)

A DSP based 10BaseT/100BaseTX Ethernet transceiver in a 1.8 V, 0.18 μm CMOS technology. - Scott D. Huss; Mark Mullen; C. Thomas Gray; Randall Smith; Mark Summers; Jeff Shafer; Pat Heron; Tim Sawinska; Joe Medero (CICC, 2001)

A 0.54pJ/b 20Gb/s ground-referenced single-ended short-haul serial link in 28nm CMOS for advanced packaging applications. - John W. Poulton; William J. Dally; Xi Chen 033; John G. Eyles; Thomas H. Greer; Stephen G. Tell; C. Thomas Gray (ISSCC, 2013)

A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging Applications. - John W. Poulton; William J. Dally; Xi Chen 033; John G. Eyles; Thomas H. Greer; Stephen G. Tell; John M. Wilson 002; C. Thomas Gray (IEEE J. Solid State Circuits, 2013)

A reverse write assist circuit for SRAM dynamic write VMIN tracking using canary SRAMs. - Arijit Banerjee 002; Mahmut E. Sinangil; John W. Poulton; C. Thomas Gray; Benton H. Calhoun (ISQED, 2014)

8.6 A 6.5-to-23.3fJ/b/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with clock forwarding and low-crosstalk contraflow wiring. - John M. Wilson 002; Matthew R. Fojtik; John W. Poulton; Xi Chen 033; Stephen G. Tell; Thomas H. Greer; C. Thomas Gray; William J. Dally (ISSCC, 2016)

A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation. - Mahmut E. Sinangil; John W. Poulton; Matthew R. Fojtik; Thomas H. Greer; Stephen G. Tell; Andreas J. Gotterba; Jesse Wang; Jason Golbus; Brian Zimmer; William J. Dally; C. Thomas Gray (IEEE J. Solid State Circuits, 2016)

A 256kb 6T self-tuning SRAM with extended 0.38V-1.2V operating range using multiple read/write assists and VMIN tracking canary sensors. - Arijit Banerjee 002; Ningxi Liu; Harsh N. Patel; Benton H. Calhoun; John W. Poulton; C. Thomas Gray (CICC, 2017)

A 25 Gb/s 470 μW active inductor equalizer for ground referenced signaling receivers. - Laura Fick; Dennis Sylvester; John W. Poulton; John M. Wilson 002; C. Thomas Gray (ISCAS, 2017)

A switching linear regulator based on a fast-self-clocked comparator with very low probability of meta-stability and a parallel analog ripple control module. - Sudhir S. Kudva; Sanquan Song; John W. Poulton; John M. Wilson 002; Wenxu Zhao; C. Thomas Gray (CICC, 2018)

Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects. - Walker J. Turner; John W. Poulton; John M. Wilson 002; Xi Chen 033; Stephen G. Tell; Matthew Fojtik; Thomas H. Greer; Brian Zimmer; Sanquan Song; Nikola Nedovic; Sudhir S. Kudva; Sunil R. Sudhakaran; et al. (CICC, 2018)

A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator. - John M. Wilson 002; Walker J. Turner; John W. Poulton; Brian Zimmer; Xi Chen 033; Sudhir S. Kudva; Sanquan Song; Stephen G. Tell; Nikola Nedovic; Wenxu Zhao; Sunil R. Sudhakaran; C. Thomas Gray; et al. (ISSCC, 2018)

Hardware-Enabled Artificial Intelligence. - William J. Dally; C. Thomas Gray; John Poulton; Brucek Khailany; John M. Wilson 002; Larry R. Dennison (VLSI Circuits, 2018)

Voltage-Follower Coupling Quadrature Oscillator with Embedded Phase-Interpolator in 16nm FinFET. - Xi Chen 033; Sanquan Song; John Poulton; Nikola Nedovic; Brian Zimmer; Stephen G. Tell; C. Thomas Gray (CICC, 2019)

A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET. - Sanquan Song; John Poulton; Xi Chen 033; Brian Zimmer; Stephen G. Tell; Walker J. Turner; Sudhir S. Kudva; Nikola Nedovic; John M. Wilson 002; C. Thomas Gray; William J. Dally (CICC, 2019)

Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference. - Angad S. Rekhi; Brian Zimmer; Nikola Nedovic; Ningxi Liu; Rangharajan Venkatesan; Miaorong Wang; Brucek Khailany; William J. Dally; C. Thomas Gray (DAC, 2019)

A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology. - Rangharajan Venkatesan; Yakun Sophia Shao; Brian Zimmer; Jason Clemons; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (Hot Chips Symposium, 2019)

Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture. - Yakun Sophia Shao; Jason Clemons; Rangharajan Venkatesan; Brian Zimmer; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (MICRO, 2019)

A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm. - Brian Zimmer; Rangharajan Venkatesan; Yakun Sophia Shao; Jason Clemons; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (VLSI Circuits, 2019)

A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator. - John W. Poulton; John M. Wilson 002; Walker J. Turner; Brian Zimmer; Xi Chen 033; Sudhir S. Kudva; Sanquan Song; Stephen G. Tell; Nikola Nedovic; Wenxu Zhao; Sunil R. Sudhakaran; C. Thomas Gray; et al. (IEEE J. Solid State Circuits, 2019)

6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links. - Xi Chen 033; Nikola Nedovic; Stephen G. Tell; Sudhir S. Kudva; Brian Zimmer; Thomas H. Greer; John W. Poulton; Sanquan Song; Walker J. Turner; John M. Wilson 002; C. Thomas Gray (ISSCC, 2020)

A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm. - Brian Zimmer; Rangharajan Venkatesan; Yakun Sophia Shao; Jason Clemons; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (IEEE J. Solid State Circuits, 2020)

A 77 MHz Relaxation Oscillator in 5nm FinFET with 3ns TIE over 10K cycles and ±0.3% Thermal Stability using Frequency-Error Feedback Loop. - Nandish Mehta; Stephen G. Tell; Walker J. Turner; Lamar Tatro; Giant Goh; C. Thomas Gray (A-SSCC, 2021)

Simba: scaling deep-learning inference with chiplet-based architecture. - Yakun Sophia Shao; Jason Clemons; Rangharajan Venkatesan; Brian Zimmer; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (Commun. ACM, 2021)

AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies. - Hao Chen 059; Walker J. Turner; Sanquan Song; Keren Zhu 001; George F. Kokai; Brian Zimmer; C. Thomas Gray; Brucek Khailany; David Z. Pan; Haoxing Ren (ISPD, 2022)

A 17-95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm. - Ben Keller; Rangharajan Venkatesan; Steve Dai; Stephen G. Tell; Brian Zimmer; William J. Dally; C. Thomas Gray; Brucek Khailany (VLSI Technology and Circuits, 2022)

A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS. - Yoshinori Nishi; John W. Poulton; Xi Chen 033; Sanquan Song; Brian Zimmer; Walker J. Turner; Stephen G. Tell; Nikola Nedovic; John M. Wilson 002; William J. Dally; C. Thomas Gray (VLSI Technology and Circuits, 2022)

An FLL-Based Clock Glitch Detector for Security Circuits in a 5nm FINFET Process. - Sanquan Song; Stephen G. Tell; Brian Zimmer; Sudhir S. Kudva; Nikola Nedovic; C. Thomas Gray (VLSI Technology and Circuits, 2022)

An On-Chip Relaxation Oscillator in 5-nm FinFET Using a Frequency-Error Feedback Loop. - Nandish Mehta; Stephen G. Tell; Walker J. Turner; Lamar Tatro; Jih Ren Goh; C. Thomas Gray (IEEE J. Solid State Circuits, 2022)

A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm. - Ben Keller; Rangharajan Venkatesan; Steve Dai; Stephen G. Tell; Brian Zimmer; Charbel Sakr; William J. Dally; C. Thomas Gray; Brucek Khailany (IEEE J. Solid State Circuits, 2023)

A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS. - Yoshinori Nishi; John W. Poulton; Walker J. Turner; Xi Chen 033; Sanquan Song; Brian Zimmer; Stephen G. Tell; Nikola Nedovic; John M. Wilson 002; William J. Dally; C. Thomas Gray (IEEE J. Solid State Circuits, 2023)

A Distributed Power Supply Scheme with Dropout Voltage in Range 6mv-500mv and a Low Overhead Retention Mode. - Siddharth Saxena; Sudhir S. Kudva; Vijay Srinivasan; Miguel Rodriguez; Walter Li; Shalimar Rasheed; Gaurav Ajwani; Tezaswi Raja; Santosh A; C. Thomas Gray (CICC, 2024)

Leveraging Micro-Bump Pitch Scaling to Accelerate Interposer Link Bandwidths for Future High-Performance Compute Applications. - Walker J. Turner; John W. Poulton; Yoshinori Nishi; Xi Chen 033; Brian Zimmer; Sanquan Song; John M. Wilson 002; William J. Dally; C. Thomas Gray (CICC, 2024)

16.4 High-Density and Low-Power PUF Designs in 5nm Achieving 23× and 39× BER Reduction After Unstable Bit Detection and Masking. - Sudhir S. Kudva; Mahmut Ersin Sinangil; Stephen G. Tell; Nikola Nedovic; Sanquan Song; Brian Zimmer; C. Thomas Gray (ISSCC, 2024)

A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS. - Yoshinori Nishi; John W. Poulton; Walker J. Turner; Xi Chen 033; Sanquan Song; Brian Zimmer; Stephen G. Tell; Nikola Nedovic; John M. Wilson 002; William J. Dally; C. Thomas Gray (IEEE J. Solid State Circuits, 2024)

17.6 A 100MHz Self-Calibrating RC Oscillator Capable of Clock-Glitch Detection for Hardware Security in a 3nm FinFET Process. - Nandish Mehta; Stephen G. Tell; Sanquan Song; Sudhir S. Kudva; Brian Zimmer; Mahmut E. Sinangil; C. Thomas Gray (ISSCC, 2025)