Test vector encoding using partial LFSR reseeding. - C. V. Krishna; Abhijit Jas; Nur A. Touba (ITC, 2001)

Hybrid BIST Based on Weighted Pseudo-Random Testing: A New Test Resource Partitioning Scheme. - Abhijit Jas; C. V. Krishna; Nur A. Touba (VTS, 2001)

A methodology for automated insertion of concurrent error detection hardware in synthesizable Verilog RTL. - Kartik Mohanram; C. V. Krishna; Nur A. Touba (ISCAS (1), 2002)

Reducing Test Dat Volume Using LFSR Reseeding with Seed Compression. - C. V. Krishna; Nur A. Touba (ITC, 2002)

Hybrid BIST Using an Incrementally Guided LFSR. - C. V. Krishna; Nur A. Touba (DFT, 2003)

Adjustable Width Linear Combinational Scan Vector Decompression. - C. V. Krishna; Nur A. Touba (ICCAD, 2003)

3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme. - C. V. Krishna; Nur A. Touba (VTS, 2004)

Achieving high encoding efficiency with partial dynamic LFSR reseeding. - C. V. Krishna; Abhijit Jas; Nur A. Touba (ACM Trans. Design Autom. Electr. Syst., 2004)

Weighted pseudorandom hybrid BIST. - Abhijit Jas; C. V. Krishna; Nur A. Touba (IEEE Trans. Very Large Scale Integr. Syst., 2004)