Resource constrained dataflow retiming heuristics for VLIW ASIPs. - Margarida F. Jacome; Gustavo de Veciana; Cagdas Akturan (CODES, 1999)

FDRA: A Software-Pipelining Algorithm for Embedded VLIW Processors. - Cagdas Akturan; Margarida F. Jacome (ISSS, 2000)

CALiBeR: A Software Pipelining Algorithm for Clustered Embedded VLIW Processors. - Cagdas Akturan; Margarida F. Jacome (ICCAD, 2001)

An Effective Software Pipelining Algorithm for Clustered Embedded VLIW Processors. - Cagdas Akturan; Margarida F. Jacome (Des. Autom. Embed. Syst., 2002)

RS-FDRA: A register-sensitive software pipelining algorithm for embedded VLIW processors. - Cagdas Akturan; Margarida F. Jacome (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)